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DSCC-DWG-85078 REV D
DELAY LINES, ACTIVE, PROGRAMMABLE 3 BIT, 16 PIN DIP COMPATIBLE, EMITTER-COUPLED LOGIC (ECL)
| contributor author | DLA - CC - DLA Land and Maritime | |
| date accessioned | 2017-09-04T17:07:56Z | |
| date available | 2017-09-04T17:07:56Z | |
| date copyright | 06/23/2008 | |
| date issued | 2008 | |
| identifier other | BZHKGCAAAAAAAAAA.pdf | |
| identifier uri | https://yse.yabesh.ir/std/handle/yse/131523 | |
| description abstract | This drawing describes the requirements for a family of programmable 3 bit, 16 pin compatible, emitter-coupled logic (ECL) delay lines.Intended Use: Devices conforming to this drawing are intended for use when military specifications do not exist and qualified military devices that will perform the required function are not available for OEM application. | |
| language | English | |
| title | DSCC-DWG-85078 REV D | num |
| title | DELAY LINES, ACTIVE, PROGRAMMABLE 3 BIT, 16 PIN DIP COMPATIBLE, EMITTER-COUPLED LOGIC (ECL) | en |
| type | standard | |
| page | 10 | |
| status | Active | |
| tree | DLA - CC - DLA Land and Maritime:;2008 | |
| contenttype | fulltext |
