IEEE 1076.4

Behavioural languages Part 5: VITAL ASIC (application specific integrated circuit) modeling specification - IEEE Computer Society Document

contributor author	IEEE - The Institute of Electrical and Electronics Engineers, Inc.
date accessioned	2017-09-04T18:15:52Z
date available	2017-09-04T18:15:52Z
date copyright	38261
date issued	2004
identifier other	HLKWGBAAAAAAAAAA.pdf
identifier uri	https://yse.yabesh.ir/std/handle/yse/198779
description abstract	To provide a standard method of modeling ASICs in VHDL. This method is aimed at providing efficient, accurate, and tool independent simulation suitable for large chip-level designs typical of those which are based on ASICs. Purpose Current industry methods for designing complex chip-level designs rely on proprietary solutions which are based on specific commercial tools. This standard provides an effective means of performing those designs in a standard, non-proprietary manner that is independent of specific tools. This promotes cost effective design flows and promotes healthy levels of competition in the electronic design industry. This standard builds on the work of IEEE 1076 VHDL which is a standard hardware description language designed to allow such tool independent electronic design.
language	English
title	IEEE 1076.4	num
title	Behavioural languages Part 5: VITAL ASIC (application specific integrated circuit) modeling specification - IEEE Computer Society Document	en
type	standard
page	436
status	Active
tree	IEEE - The Institute of Electrical and Electronics Engineers, Inc.:;2004
contenttype	fulltext