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JEDEC JESD8-6
High Speed Transceiver Logic (HSTL) A 1.5V Output Buffer Supply Voltage Based Interface Standard for Digital Integrated Circuits
| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T15:17:27Z | |
| date available | 2017-09-04T15:17:27Z | |
| date copyright | 01/01/1995 | |
| date issued | 1995 | |
| identifier other | MNCHCAAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std/handle/yse/16904 | |
| description abstract | This standard is a 1.5 volt high performance CMOS-based interface document suitable for high I/O count CMOS and BiCMOS devices operating at frequencies in excess of 200 Mhz. | |
| language | English | |
| title | JEDEC JESD8-6 | num |
| title | High Speed Transceiver Logic (HSTL) A 1.5V Output Buffer Supply Voltage Based Interface Standard for Digital Integrated Circuits | en |
| type | standard | |
| page | 20 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;1995 | |
| contenttype | fulltext | |
| subject keywords | BiCMOS | |
| subject keywords | CMOS | |
| subject keywords | High Speed Transceiver Logic - HSTL | |
| subject keywords | Output Buffer Supply Voltage |
