JEDEC JEP122G

Failure Mechanisms and Models for Semiconductor Devices

contributor author	JEDEC - Solid State Technology Association
date accessioned	2017-09-04T15:38:22Z
date available	2017-09-04T15:38:22Z
date copyright	40817
date issued	2011
identifier other	AZJFOEAAAAAAAAAA.pdf
identifier uri	http://yse.yabesh.ir/std/handle/yse/40434
description abstract	This publication provides a list of failure mechanisms and their associated activation energies or acceleration factors that may be used in making system failure rate estimations when the only available data is based on tests performed at accelerated stress test conditions. The method to be used is the Sum-of-the-Failure-Rates method. The models apply primarily to the following: a) Aluminum (doped with small amounts of Cu and/or Si) and copper alloy metallization b) Refractory metal barrier metals with thin anti-reflection coatings c) Doped silica or silicon nitride interlayer dielectrics, including low dielectric constant materials d) Poly silicon or "salicide" gates (metal-rich silicides such as W, Ni & Co to decrease resistivity) e) Thin SiO₂ gate dielectric f) Silicon with p-n junction isolation g) Tin Whisker Growth Kinetics h) Printed Circuit Board Ionic Mobility
language	English
title	JEDEC JEP122G	num
title	Failure Mechanisms and Models for Semiconductor Devices	en
type	standard
page	108
status	Active
tree	JEDEC - Solid State Technology Association:;2011
contenttype	fulltext