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JEDEC JESD75-1
Ball Grid Array Pinouts Standardized for 16, 18 and 20-Bit Logic Functions Using a 54 Ball Package
| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T15:40:42Z | |
| date available | 2017-09-04T15:40:42Z | |
| date copyright | 37165 | |
| date issued | 2001 | |
| identifier other | PEOCTAAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std/handle/yse/42905 | |
| description abstract | This standard establishes a 54 Ball Grid Array pinout for 16, 18 and 20-bit standard logic devices that are currently being produced in 48 and 56 Pin SSOP and TSSOP packages. The 54 Ball Grid Array Package is organized as a 6 x 9 array with balls on a .8mm x .8mm grid pitch. | |
| language | English | |
| title | JEDEC JESD75-1 | num |
| title | Ball Grid Array Pinouts Standardized for 16, 18 and 20-Bit Logic Functions Using a 54 Ball Package | en |
| type | standard | |
| page | 10 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;2001 | |
| contenttype | fulltext | |
| subject keywords | 54 Ball Package | |
| subject keywords | Ball Grid Array | |
| subject keywords | BGA | |
| subject keywords | Logic Functions | |
| subject keywords | Pinouts |
