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GRAPHICS DOUBLE DATA RATE (GDDR5) SGRAM STANDARD

contributor authorJEDEC - Solid State Technology Association
date accessioned2017-09-04T15:07:10Z
date available2017-09-04T15:07:10Z
date copyright09/01/2013
date issued2013
identifier otherLHDHGFAAAAAAAAAA.pdf
identifier urihttp://yse.yabesh.ir/std/handle/yse/4853
description abstractThis document defines the Graphics Double Data Rate 5 (GDDR5) Synchronous Graphics Random Access Memory (SGRAM) standard, including features, functionality, package, and pin assignments. This scope may be expanded in future to also include other higher density devices.
The purpose of this Standard is to define the minimum set of requirements for JEDEC standard compatible 512 Mb through 8 Gb x32 GDDR5 SGRAM devices. System designs based on the required aspects of this standard will be supported by all GDDR5 SGRAM vendors providing JEDEC standard compatible devices. Some aspects of the GDDR5 standard such as AC timings and capacitance values were not standardized. Some features are optional and therefore may vary among vendors. In all cases, vendor data sheets should be consulted for specifics.
This standard was created based on the DDR Standard (JESD79) and some aspects of the GDDR4 Standard (JESD21C - 3.11.5.8). Each aspect of the changes for high speed operation were considered and balloted. The accumulation of these ballots were then incorporated to prepare this GDDR5 SGRAM document, replacing whole sections and incorporating the changes into Functional Description and Operation.
languageEnglish
titleJEDEC JESD212Bnum
titleGRAPHICS DOUBLE DATA RATE (GDDR5) SGRAM STANDARDen
typestandard
page154
statusActive
treeJEDEC - Solid State Technology Association:;2013
contenttypefulltext


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