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French -- Circuits intégrés – Circuits intégrés tridimensionnels – Partie 1: Terminologie - Edition 1.0|English -- Integrated circuits – Three dimensional integrated circuits – Part 1: Terminology - Edition 1.0
IEC 63011-1
Organization:
IEC - International Electrotechnical Commission
Year: 2018
Abstract: Scope: This part of IEC 63011 provides definitions pertaining to multichip integrated circuits, as vertically stacked dies using through-silicon vias (TSVs) or micro bumps. Terms and definitions related to the fabrication and test of the multichip integrated circuits are also provided.
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French -- Circuits intégrés – Circuits intégrés tridimensionnels – Partie 1: Terminologie - Edition 1.0|English -- Integrated circuits – Three dimensional integrated circuits – Part 1: Terminology - Edition 1.0
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| contributor author | IEC - International Electrotechnical Commission | |
| date accessioned | 2020-09-15T22:28:27Z | |
| date available | 2020-09-15T22:28:27Z | |
| date copyright | 2018.11.01 | |
| date issued | 2018 | |
| identifier other | UFGOGGAAAAAAAAAA.pdf | |
| identifier other | UFGOGGAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std;jsein/handle/yse/289033 | |
| description abstract | Scope: This part of IEC 63011 provides definitions pertaining to multichip integrated circuits, as vertically stacked dies using through-silicon vias (TSVs) or micro bumps. Terms and definitions related to the fabrication and test of the multichip integrated circuits are also provided. | |
| language | English, French | |
| title | French -- Circuits intégrés – Circuits intégrés tridimensionnels – Partie 1: Terminologie - Edition 1.0|English -- Integrated circuits – Three dimensional integrated circuits – Part 1: Terminology - Edition 1.0 | en |
| title | IEC 63011-1 | num |
| type | standard | |
| page | 28 | |
| status | Active | |
| tree | IEC - International Electrotechnical Commission:;2018 | |
| contenttype | fulltext |