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IPC IPC/EIA J-STD-026
Semiconductor Design Standard for Flip Chip Applications
Organization:
IPC - Association Connecting Electronics Industries
Year: 1999
Abstract: This standard addresses semiconductor chip design. It is intended for applications utilizing standard substrates, materials, assembly, and test methods as well as established semiconductor fabrication and bumping processes.
Purpose
The purpose is to provide flip chip design standards which are commensurate with established fabrication, bump, test, assembly, handling and application practices. Addressed are electrical, thermal, and mechanical chip design parameters and methodologies as well as the reliability associated with these items. These standards are intended for new designs as well as modifications of non-flip chip designs.
Purpose
The purpose is to provide flip chip design standards which are commensurate with established fabrication, bump, test, assembly, handling and application practices. Addressed are electrical, thermal, and mechanical chip design parameters and methodologies as well as the reliability associated with these items. These standards are intended for new designs as well as modifications of non-flip chip designs.
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IPC IPC/EIA J-STD-026
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| contributor author | IPC - Association Connecting Electronics Industries | |
| date accessioned | 2017-09-04T17:19:35Z | |
| date available | 2017-09-04T17:19:35Z | |
| date copyright | 08/01/1999 | |
| date issued | 1999 | |
| identifier other | ZNSHKAAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std;jsery=authoF2376596FCDCAC426159DD6E273C9FCD/handle/yse/142800 | |
| description abstract | This standard addresses semiconductor chip design. It is intended for applications utilizing standard substrates, materials, assembly, and test methods as well as established semiconductor fabrication and bumping processes. Purpose The purpose is to provide flip chip design standards which are commensurate with established fabrication, bump, test, assembly, handling and application practices. Addressed are electrical, thermal, and mechanical chip design parameters and methodologies as well as the reliability associated with these items. These standards are intended for new designs as well as modifications of non-flip chip designs. | |
| language | English | |
| title | IPC IPC/EIA J-STD-026 | num |
| title | Semiconductor Design Standard for Flip Chip Applications | en |
| type | standard | |
| page | 48 | |
| status | Active | |
| tree | IPC - Association Connecting Electronics Industries:;1999 | |
| contenttype | fulltext |