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French -- Circuits intégrés – Circuits intégrés tridimensionnels – Partie 2: Alignement de puces empilées à petits pas d'interconnexion - Edition 1.0|English -- Integrated circuits – Three dimensional integrated circuits – Part 2: Alignment of stacked dies having fine pitch interconnect - Edition 1.0
IEC 63011-2
Organization:
IEC - International Electrotechnical Commission
Year: 2018
Abstract: Scope: This part of IEC 63011 provides specifications of initial alignment and alignment maintenance between multiple stacked integrated circuits during the die bonding process. These specifications define the alignment keys and operating procedures of the keys. These specifications apply only if electrical coupling method of die-to-die alignment is used in the die stacking.
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French -- Circuits intégrés – Circuits intégrés tridimensionnels – Partie 2: Alignement de puces empilées à petits pas d'interconnexion - Edition 1.0|English -- Integrated circuits – Three dimensional integrated circuits – Part 2: Alignment of stacked dies having fine pitch interconnect - Edition 1.0
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| contributor author | IEC - International Electrotechnical Commission | |
| date accessioned | 2020-09-15T22:28:36Z | |
| date available | 2020-09-15T22:28:36Z | |
| date copyright | 2018.11.01 | |
| date issued | 2018 | |
| identifier other | XFGOGGAAAAAAAAAA.pdf | |
| identifier other | XFGOGGAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std;query=autho1826AF679D40527369727A00D52FAB6A0Facilities%20Engineering%20Command%226EFDEC9FCD/handle/yse/289072 | |
| description abstract | Scope: This part of IEC 63011 provides specifications of initial alignment and alignment maintenance between multiple stacked integrated circuits during the die bonding process. These specifications define the alignment keys and operating procedures of the keys. These specifications apply only if electrical coupling method of die-to-die alignment is used in the die stacking. | |
| language | English, French | |
| title | French -- Circuits intégrés – Circuits intégrés tridimensionnels – Partie 2: Alignement de puces empilées à petits pas d'interconnexion - Edition 1.0|English -- Integrated circuits – Three dimensional integrated circuits – Part 2: Alignment of stacked dies having fine pitch interconnect - Edition 1.0 | en |
| title | IEC 63011-2 | num |
| type | standard | |
| page | 32 | |
| status | Active | |
| tree | IEC - International Electrotechnical Commission:;2018 | |
| contenttype | fulltext |