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JEDEC JEP158

3D Chip Stack with Through-Silicon Vias (TSVS): Identifying, Evaluating and Understanding Reliability Interactions

contributor authorJEDEC - Solid State Technology Association
date accessioned2017-09-04T16:55:06Z
date available2017-09-04T16:55:06Z
date copyright40118
date issued2009
identifier otherXAOKPCAAAAAAAAAA.pdf
identifier urihttp://yse.yabesh.ir/std;quein=autho123393FD081DAC4/handle/yse/118616
description abstractTo increase device bandwidth, reduce power and shrink form factor, microelectronics manufacturers are implementing three dimensional (3D) chip stacking using through silicon vias (TSVs). Chip stacking with TSVs combines silicon and packaging technologies. As a result, these new structures have unique reliability requirements. This document is a guideline that describes how to evaluate the reliability of 3D TSV silicon assemblies.
languageEnglish
titleJEDEC JEP158num
title3D Chip Stack with Through-Silicon Vias (TSVS): Identifying, Evaluating and Understanding Reliability Interactionsen
typestandard
page24
statusActive
treeJEDEC - Solid State Technology Association:;2009
contenttypefulltext
subject keywords3D
subject keywordsConnection
subject keywordsReliabilty
subject keywordsStack
subject keywordsThrough-Silicon Via
subject keywordsVia


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