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JEDEC JEP158
3D Chip Stack with Through-Silicon Vias (TSVS): Identifying, Evaluating and Understanding Reliability Interactions
Organization:
JEDEC - Solid State Technology Association
Year: 2009
Abstract: To increase device bandwidth, reduce power and shrink form factor, microelectronics manufacturers are implementing three dimensional (3D) chip stacking using through silicon vias (TSVs). Chip stacking with TSVs combines silicon and packaging technologies. As a result, these new structures have unique reliability requirements. This document is a guideline that describes how to evaluate the reliability of 3D TSV silicon assemblies.
Subject: 3D
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| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T16:55:06Z | |
| date available | 2017-09-04T16:55:06Z | |
| date copyright | 40118 | |
| date issued | 2009 | |
| identifier other | XAOKPCAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std;quein=autho123393FD081DAC4/handle/yse/118616 | |
| description abstract | To increase device bandwidth, reduce power and shrink form factor, microelectronics manufacturers are implementing three dimensional (3D) chip stacking using through silicon vias (TSVs). Chip stacking with TSVs combines silicon and packaging technologies. As a result, these new structures have unique reliability requirements. This document is a guideline that describes how to evaluate the reliability of 3D TSV silicon assemblies. | |
| language | English | |
| title | JEDEC JEP158 | num |
| title | 3D Chip Stack with Through-Silicon Vias (TSVS): Identifying, Evaluating and Understanding Reliability Interactions | en |
| type | standard | |
| page | 24 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;2009 | |
| contenttype | fulltext | |
| subject keywords | 3D | |
| subject keywords | Connection | |
| subject keywords | Reliabilty | |
| subject keywords | Stack | |
| subject keywords | Through-Silicon Via | |
| subject keywords | Via |