JEDEC JESD24-2

Gate Charge Test Method - Addendum to JEDEC JESD 24

contributor author	JEDEC - Solid State Technology Association
date accessioned	2017-09-04T17:08:38Z
date available	2017-09-04T17:08:38Z
date copyright	01/01/1991 (R 2002)
date issued	2002
identifier other	YKTZJBAAAAAAAAAA.pdf
identifier uri	http://yse.yabesh.ir/std;quein=autho123393FD081DAC4/handle/yse/132105
description abstract	This addendum establishes a method for measuring power device gate charge. A gate charge test is performed by driving the device gate with a constant current and measuring the resulting gate voltage response. Constant gate current scales the gate voltage, a function of time, to a function of coulombs. The slope of the generated response reflects the active device capacitance as it varies during the switching transition . Gate charge measurements are useful for characterizing the large signal switching performance of power MOS and IGBT devices. Developed over a four year span by the JEDEC JC-25 Committee, the method defines a repeatable means of measuring the widely published Qgd charge values.
language	English
title	JEDEC JESD24-2	num
title	Gate Charge Test Method - Addendum to JEDEC JESD 24	en
type	standard
page	14
status	Active
tree	JEDEC - Solid State Technology Association:;2002
contenttype	fulltext
subject keywords	Gate Charge
subject keywords	Test Method - Gate Charge