JEDEC JEP159

Abstract

The continued scaling of advanced VLSI circuits, particularly of high performance logic circuits, is driving the need for low-<em>k</em> materials and copper metallization in back end of the line (BEOL) interconnect systems to reduce the resistance-capacitance (RC) delay, cross talk noise, and power dissipation. With the wide applications of low-<em>k</em> and ultra-low-<em>k</em> dielectric materials at the 90nm technology node and beyond, the long-term reliability of such materials is rapidly becoming one of the most critical challenges for technology qualification. Low-k time dependent dielectric breakdown (TDDB) is commonly considered as an important reliability issue because low-<em>k</em> materials generally have weaker intrinsic breakdown strength than traditional SiO₂ dielectrics. This problem is further exacerbated by the aggressive shrinking of the interconnect pitch size due to continuous technology scaling. <br>The procedures outlined herein were developed to estimate the electrical breakdown performance of low-k ILD and as a tool for driving constant improvement in the low-k ILD process. The test procedure described within this document should be used as common methodologies for low-k ILD process control and improvement and could be used as a guideline to predict lifetime or the failure rate of a semiconductor product. In actual practice the ILD TDDB reliability of a semiconductor product is a complicated function of the interconnect critical area, power duty cycles, transient voltage variation, and series resistance. These parameters are not considered within this document. <br>The purpose of this document is to describe test procedures for characterizing the reliability of inter/intra level dielectrics. It does not specify acceptance or rejection criteria for any of the described procedures.