درباره ما
JEDEC JEP159
Procedure for the Evaluation of Low-k/Metal Inter/Intra-Level Dielectric Integrity
Organization:
JEDEC - Solid State Technology Association
Year: 2010
Abstract: The continued scaling of advanced VLSI circuits, particularly of high performance logic circuits, is driving the need for low-k materials and copper metallization in back end of the line (BEOL) interconnect systems to reduce the resistance-capacitance (RC) delay, cross talk noise, and power dissipation. With the wide applications of low-k and ultra-low-k dielectric materials at the 90nm technology node and beyond, the long-term reliability of such materials is rapidly becoming one of the most critical challenges for technology qualification. Low-k time dependent dielectric breakdown (TDDB) is commonly considered as an important reliability issue because low-k materials generally have weaker intrinsic breakdown strength than traditional SiO2 dielectrics. This problem is further exacerbated by the aggressive shrinking of the interconnect pitch size due to continuous technology scaling.
The procedures outlined herein were developed to estimate the electrical breakdown performance of low-k ILD and as a tool for driving constant improvement in the low-k ILD process. The test procedure described within this document should be used as common methodologies for low-k ILD process control and improvement and could be used as a guideline to predict lifetime or the failure rate of a semiconductor product. In actual practice the ILD TDDB reliability of a semiconductor product is a complicated function of the interconnect critical area, power duty cycles, transient voltage variation, and series resistance. These parameters are not considered within this document.
The purpose of this document is to describe test procedures for characterizing the reliability of inter/intra level dielectrics. It does not specify acceptance or rejection criteria for any of the described procedures.
The procedures outlined herein were developed to estimate the electrical breakdown performance of low-k ILD and as a tool for driving constant improvement in the low-k ILD process. The test procedure described within this document should be used as common methodologies for low-k ILD process control and improvement and could be used as a guideline to predict lifetime or the failure rate of a semiconductor product. In actual practice the ILD TDDB reliability of a semiconductor product is a complicated function of the interconnect critical area, power duty cycles, transient voltage variation, and series resistance. These parameters are not considered within this document.
The purpose of this document is to describe test procedures for characterizing the reliability of inter/intra level dielectrics. It does not specify acceptance or rejection criteria for any of the described procedures.
Collections
:
Show full item record
| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T17:18:16Z | |
| date available | 2017-09-04T17:18:16Z | |
| date copyright | 08/01/2010 | |
| date issued | 2010 | |
| identifier other | ZKMTZCAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std;quein=autho123393FD081DAC4/handle/yse/141628 | |
| description abstract | The continued scaling of advanced VLSI circuits, particularly of high performance logic circuits, is driving the need for low-k materials and copper metallization in back end of the line (BEOL) interconnect systems to reduce the resistance-capacitance (RC) delay, cross talk noise, and power dissipation. With the wide applications of low-k and ultra-low-k dielectric materials at the 90nm technology node and beyond, the long-term reliability of such materials is rapidly becoming one of the most critical challenges for technology qualification. Low-k time dependent dielectric breakdown (TDDB) is commonly considered as an important reliability issue because low-k materials generally have weaker intrinsic breakdown strength than traditional SiO2 dielectrics. This problem is further exacerbated by the aggressive shrinking of the interconnect pitch size due to continuous technology scaling. The procedures outlined herein were developed to estimate the electrical breakdown performance of low-k ILD and as a tool for driving constant improvement in the low-k ILD process. The test procedure described within this document should be used as common methodologies for low-k ILD process control and improvement and could be used as a guideline to predict lifetime or the failure rate of a semiconductor product. In actual practice the ILD TDDB reliability of a semiconductor product is a complicated function of the interconnect critical area, power duty cycles, transient voltage variation, and series resistance. These parameters are not considered within this document. The purpose of this document is to describe test procedures for characterizing the reliability of inter/intra level dielectrics. It does not specify acceptance or rejection criteria for any of the described procedures. | |
| language | English | |
| title | JEDEC JEP159 | num |
| title | Procedure for the Evaluation of Low-k/Metal Inter/Intra-Level Dielectric Integrity | en |
| type | standard | |
| page | 24 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;2010 | |
| contenttype | fulltext |