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Browsing JEDEC - Solid State Technology Association by Issue Date
Now showing items 1-20 of 369
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JEDEC JEB15
Abstract: This bulletin explains the terminology and methods of measurement for bistable semiconductor microcircuits. It is also intended to be used with the EIA Registration Data Format for semiconductor integrated bistable logic ...Subject(s) : Letter Symbols , Quick Reference Guide , Symbols - Quick Reference Guide Data Sheet Disclaimers , -
JEDEC JEP79
Abstract: This publication is for photoconductive cells sensitive primarily in the visible and near infrared region.Subject(s) : Cells - Photoconductive , Photoconductive Cells , Test Method - Photoconductive Cells , -
JEDEC JEP78
Abstract: The intent of this publication is to facilitate the specification of infrared detector diodes, particularly in conjunction with the preparation of data for JEDEC type registration.Subject(s) : Detectors - Infrared , Infrared - Detectors , Spectral Response Curves , -
JEDEC JEB19
Abstract: This recommendation applies to MOS Shift Registers. Definitions are given for P-channel registers but are applicable to all CMOS and N-channel with changes in power supply notation. -
JEDEC TENTSTD12
Abstract: The suppresser furnished under this standard shall be a product that has been tested and meets the definitions and minimum requirements specified herein. -
JEDEC EIA-397
Abstract: One section of this standard presents a thorough explanation of thyristor principals, defining thedifferent classes of these devices, their Physical structure and detailing the numerous test methods and ratings required ...Subject(s) : Test Method - Thyristors , Thyristors , -
JEDEC EIA-397-1
Abstract: A compilation of 12 new or revised thyristor test methods which have been adopted since the original standard was issued in 1972.Subject(s) : Thyristor Test Methods , -
JEDEC JESD13-B
Abstract: This standard provides for uniformity, multiplicity of sources, elimination of confusion, and ease of device specifications and system design by users. It gives electrical levels and timing diagrams for B Series CMOS devices.Subject(s) : B Series - CMOS Devices , CMOS Devices - B Series , Electrical Levels - B Series CMOS Devices , Timing Diagrams - B Series CMOS Devices , -
JEDEC JEP65
Abstract: This publication describes tests which are intended to represent the verification of maximum ratings for data sheets; they are not tests for performance or quality level. This material is to be used in conjunction with ...Subject(s) : Maximum Ratings - Power Transistors , Power Transistors - Maximum Rating Verifications , -
JEDEC JESD23
Abstract: This standard specifies a collection of procedures for testing and character designation of liquid crystal devices.Subject(s) : Character Designation - LCD , Liquid Crystal Devices - LCD , Test Method - LCD , -
JEDEC JESD1
Abstract: This standard shows how to convert existing DIP pinouts for op-amps, comparators, and D/A converters, to chip carrier packages.Subject(s) : Chip Carrier - Leadless Pinouts , Leadless Pinouts - Chip Carriers , Linears , Pinouts , -
JEDEC JESD2
Abstract: This standard provides a chip carrier format for digital devices by defining pin functions and locations for 20, 38, 44, 52, and 68-terminal devices.Subject(s) : Bipolar Logic Pinouts , Chip Carriers , Digital Pinouts , -
JEDEC EIA-365
Abstract: The purpose of this standard is to classify the output of solar cells for space vehicle service in accordance with requirements of EIA Format JS4-RDF4.Subject(s) : Calibration Procedure - Solar Cells , Solar Cells , Space Vehicle Service , -
JEDEC JESD11
Abstract: This standard indicates the procedures used to convert existing DIP and flat packages for digital parts (SSI & MSI) to chip carrier packages.Subject(s) : Chip Carrier Pinouts , CMOS Devices - 4000 , Logic Circuits - HC and HCT , -
JEDEC JEB5-A
Abstract: The purpose of this bulletin is to recommend for use in the rating of semiconductor logic gating microcircuits which use the binary states to represent and process logic information. Both static and dynamic measurements ...Subject(s) : Logic Gating Microcircuits , Measurement - Static and Dynamic , -
JEDEC JESD12
Abstract: The purpose of these benchmarks is to provide a common set of high level functions which serve as vehicles for comparing the performance of gate arrays implemented in any technology using any internal structure. These ...Subject(s) : Cell Based - Integrated Circuits , Gate Array - Performance , -
JEDEC JESD24
Abstract: This standard contains a listing of terms and definitions and letter symbols; a description of established procedures that are followed in the assignment of semiconductor-industry-type designations to power transistors; ...Subject(s) : Power MOSFETs , Terms and Definitions - Power MOSFETs , Thermal Characteristics - Power MOSFETs , Transistors - Power MOSFETs , -
JEDEC JESD7-A
Abstract: This standard provides uniformity, multiplicity of sources, eliminate confusion, and ease of device specification and design by users for HC, and HCT CMOS devices. This standard specifies electrical parameters. It also ...Subject(s) : CMOS Devices - High Speed , High Speed - CMOS Devices , -
JEDEC JESD12-3
Abstract: This standard defines a minimum set of macro cell standards for CMOS gate arrays. A total of 41 macro cell types are addressed, all of which are commonly used by gate array designers to implement Application Specific ...Subject(s) : CMOS Devices - Gate Array , Gate Array , Macrocell Types , -
JEDEC JESD12-2
Abstract: The purpose of these benchmarks is to provide a common set of high level functions that serve as vehicles for comparing the performance of cell-based ICs implemented in any technology using any internal structure. JESD12-2 ...Subject(s) : Benchmark Set - Cell Based Integrated Circuits , Integrated Circuits - Cell Based ,