JEDEC JEP143C

Solid-State Reliability Assessment and Qualification Methodologies

contributor author	JEDEC - Solid State Technology Association
date accessioned	2017-09-04T15:27:37Z
date available	2017-09-04T15:27:37Z
date copyright	07/01/2012
date issued	2012
identifier other	NRXKXEAAAAAAAAAA.pdf
identifier uri	http://yse.yabesh.ir/std;quein=autho123393FD081DAC4/handle/yse/28573
description abstract	This publication applies to all integrated circuits and their associated packages. The document summarizes the suite of reliability documents and publications available. These documents address reliability qualification, reliability stress testing, and reliability modeling. The purpose of this publication is to provide an overview of some of the most commonly used systems and test methods historically performed by manufacturers to assess and qualify the reliability of solid-state products. The appropriate references to existing and proposed JEDEC or joint standards and publications are cited. This document is also intended to provide an educational background and overview of some of the technical and economic factors associated with assessing and qualifying microcircuit reliability.
language	English
title	JEDEC JEP143C	num
title	Solid-State Reliability Assessment and Qualification Methodologies	en
type	standard
page	37
status	Active
tree	JEDEC - Solid State Technology Association:;2012
contenttype	fulltext