JEDEC JESD35-2

Test Criteria for the Wafer-Level Testing of Thin Dielectrics - Addendum No. 2 to JESD35

contributor author	JEDEC - Solid State Technology Association
date accessioned	2017-09-04T15:28:45Z
date available	2017-09-04T15:28:45Z
date copyright	02/01/1996
date issued	1996
identifier other	NVLNCAAAAAAAAAAA.pdf
identifier uri	http://yse.yabesh.ir/std;quein=autho123393FD081DAC4/handle/yse/29906
description abstract	This addendum includes test criteria to supplement JESD35. JESD35 describes procedures developed for estimating the overall integrity of thin oxides in the MOS Integrated Circuit manufacturing industry. Two test procedures are included in JESD35: a Voltage-Ramp (V-Ramp) and a Current-Ramp (J-Ramp). As JESD35 became implemented into production facilities on a variety of test structures and oxide attributes, a need arose to clarify end point determination and point out some of the obstacles that could be overcome by careful characterization of the equipment and test structures.
language	English
title	JEDEC JESD35-2	num
title	Test Criteria for the Wafer-Level Testing of Thin Dielectrics - Addendum No. 2 to JESD35	en
type	standard
page	12
status	Active
tree	JEDEC - Solid State Technology Association:;1996
contenttype	fulltext
subject keywords	Test Criteria - Thin Dielectrics
subject keywords	Thin Dielectrics
subject keywords	Wafer-Level Testing