JEDEC JESD82-8.01

Standard for Definition of CU877 PLL Clock Driver for Registered DDR2 DIMM Applications

contributor author	JEDEC - Solid State Technology Association
date accessioned	2017-09-04T15:36:22Z
date available	2017-09-04T15:36:22Z
date copyright	02/01/2004
date issued	2004
identifier other	OSGYEBAAAAAAAAAA.pdf
identifier uri	http://yse.yabesh.ir/std;quein=autho123393FD081DAC4/handle/yse/38352
description abstract	This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a Â'CU877 PLL clock device for registered DDR2 DIMM applications. The purpose is to provide a standard for a Â'CU877 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This document includes minor editorial changes as noted in Annex A, page 16.
language	English
title	JEDEC JESD82-8.01	num
title	Standard for Definition of CU877 PLL Clock Driver for Registered DDR2 DIMM Applications	en
type	standard
page	22
status	Active
tree	JEDEC - Solid State Technology Association:;2004
contenttype	fulltext
subject keywords	Clock Driver
subject keywords	DDR2
subject keywords	DDR400
subject keywords	DDR533
subject keywords	PC3200
subject keywords	PLL