• 0
    • ارسال درخواست
    • حذف همه
    • Industrial Standards
    • Defence Standards
  • درباره ما
  • درخواست موردی
  • فهرست استانداردها
    • Industrial Standards
    • Defence Standards
  • راهنما
  • Login
  • لیست خرید شما 0
    • ارسال درخواست
    • حذف همه
View Item 
  •   YSE
  • Industrial Standards
  • JEDEC - Solid State Technology Association
  • View Item
  •   YSE
  • Industrial Standards
  • JEDEC - Solid State Technology Association
  • View Item
  • All Fields
  • Title(or Doc Num)
  • Organization
  • Year
  • Subject
Advanced Search
JavaScript is disabled for your browser. Some features of this site may not work without it.

Archive

JEDEC JESD75-5

SON/QFN Package Pinouts Standardized for 1-, 2-, and 3-Bit Logic Functions

Organization:
JEDEC - Solid State Technology Association
Year: 2004

Abstract: This standard defines device pinout for 1-, 2- and 3-bit wide logic functions. This pinout specifically applies to the conversion of Dual-Inline-Packaged (DIP) 1-, 2- and 3-bit logic devices to SON/QFN packaged 1-, 2- and 3-bit logic devices. The purpose of this document is to provide a pinout standard for 1-, 2- and 3-bit logic devices offered in 5-, 6- or 8-land SON/QFN packages for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.
URI: http://yse.yabesh.ir/std;quein=autho123393FD081DAC4/handle/yse/45734
Subject: 1-Bit
Collections :
  • JEDEC - Solid State Technology Association
  • Download PDF : (172.6Kb)
  • Show Full MetaData Hide Full MetaData
  • Statistics

    JEDEC JESD75-5

Show full item record

contributor authorJEDEC - Solid State Technology Association
date accessioned2017-09-04T15:43:28Z
date available2017-09-04T15:43:28Z
date copyright07/01/2004
date issued2004
identifier otherPMDQFBAAAAAAAAAA.pdf
identifier urihttp://yse.yabesh.ir/std;quein=autho123393FD081DAC4/handle/yse/45734
description abstractThis standard defines device pinout for 1-, 2- and 3-bit wide logic functions. This pinout specifically applies to the conversion of Dual-Inline-Packaged (DIP) 1-, 2- and 3-bit logic devices to SON/QFN packaged 1-, 2- and 3-bit logic devices. The purpose of this document is to provide a pinout standard for 1-, 2- and 3-bit logic devices offered in 5-, 6- or 8-land SON/QFN packages for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.
languageEnglish
titleJEDEC JESD75-5num
titleSON/QFN Package Pinouts Standardized for 1-, 2-, and 3-Bit Logic Functionsen
typestandard
page13
statusActive
treeJEDEC - Solid State Technology Association:;2004
contenttypefulltext
subject keywords1-Bit
subject keywords2-Bit
subject keywords3-Bit
subject keywordsPACKAGE PINOUTS
subject keywordsQFN
subject keywordsSON
DSpace software copyright © 2017-2020  DuraSpace
نرم افزار کتابخانه دیجیتال "دی اسپیس" فارسی شده توسط یابش برای کتابخانه های ایرانی | تماس با یابش
yabeshDSpacePersian
 
DSpace software copyright © 2017-2020  DuraSpace
نرم افزار کتابخانه دیجیتال "دی اسپیس" فارسی شده توسط یابش برای کتابخانه های ایرانی | تماس با یابش
yabeshDSpacePersian