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JEDEC JESD61A.01

Isothermal Electromigration Test Procedure

Organization:
JEDEC - Solid State Technology Association
Year: 2007

Abstract: This standard describes an algorithm for the execution of the isothermal test, using computer-controlled instrumentation. The primary use of this test is for the monitoring of microelectronic metallization lines at wafer level (1) in process development, to evaluate process options, (2) in manufacturing, to monitor metallization reliability and (3) to monitor/evaluate process equipment. While it is developed as a fast WLR test, it can also be an effective tool for complementing the reliability data obtained through the standard package level electromigration test.
URI: http://yse.yabesh.ir/std;quein=autho123393FD081DAC4/handle/yse/46229
Subject: Electromigration
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contributor authorJEDEC - Solid State Technology Association
date accessioned2017-09-04T15:43:53Z
date available2017-09-04T15:43:53Z
date copyright39356
date issued2007
identifier otherPNMVKCAAAAAAAAAA.pdf
identifier urihttp://yse.yabesh.ir/std;quein=autho123393FD081DAC4/handle/yse/46229
description abstractThis standard describes an algorithm for the execution of the isothermal test, using computer-controlled instrumentation. The primary use of this test is for the monitoring of microelectronic metallization lines at wafer level (1) in process development, to evaluate process options, (2) in manufacturing, to monitor metallization reliability and (3) to monitor/evaluate process equipment. While it is developed as a fast WLR test, it can also be an effective tool for complementing the reliability data obtained through the standard package level electromigration test.
languageEnglish
titleJEDEC JESD61A.01num
titleIsothermal Electromigration Test Procedureen
typestandard
page50
statusActive
treeJEDEC - Solid State Technology Association:;2007
contenttypefulltext
subject keywordsElectromigration
subject keywordsIsothermal
subject keywordsMetallization Lines
subject keywordsTest
subject keywordsWafer-Level
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