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A Procedure for Measuring P-Channel MOSFET Hot-Carrier- Induced Degradation Under DC Stress

contributor authorJEDEC - Solid State Technology Association
date accessioned2017-09-04T15:54:53Z
date available2017-09-04T15:54:53Z
date copyright09/01/2004
date issued2004
identifier otherQTSEGBAAAAAAAAAA.pdf
identifier urihttp://yse.yabesh.ir/std;quein=autho123393FD081DAC4/handle/yse/58289
description abstractThis method establishes a standard procedure for accelerated testing of the hot-carrier-induced change of a p-channel MOSFET. The objective is to provide a minimum set of measurements so that accurate comparisons can be made between different technologies. The measurements specified should be viewed as a starting pint in the characterization and benchmarking of the trasistor manufacturing process.
languageEnglish
titleJEDEC JESD60Anum
titleA Procedure for Measuring P-Channel MOSFET Hot-Carrier- Induced Degradation Under DC Stressen
typestandard
page24
statusActive
treeJEDEC - Solid State Technology Association:;2004
contenttypefulltext
subject keywordsCHC
subject keywordsDC Stress
subject keywordsGate Current
subject keywordsHot Carrier
subject keywordsMOSFETs
subject keywordsP-Channel - MOSFET
subject keywordsPMOS
subject keywordsTransistor


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