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JEDEC JESD22B113A
Board Level Cyclic Bend Test Method for Interconnect Reliability Characterization of SMT ICs for Handheld Electronic Products
Organization:
JEDEC - Solid State Technology Association
Year: 2012
Abstract: The Board Level Cyclic Bend Test Method is intended to evaluate and compare the performance of SMT ICs in an accelerated test environment for handheld electronic products applications. The purpose is to standardize the test methodology to provide a reproducible performance assessment of SMT ICs while duplicating the failure modes normally observed during product level test. This is not a SMT IC qualification test and is not meant to replace any product level test that may be needed to qualify a specific product and assembly.
Correlation between test and field conditions is not yet fully established. Consequently, the test procedure is presently more appropriate for relative SMT IC performance than for use as a pass/fail criterion. However, to do comparisons care must be taken to have the same test variables used, such as SMT IC configuration and size.
This publication assumes a surface mount device such as BGAs, LGAs (excluding sockets and connectors), TSOP, and CSPs. Discrete SMT devices, e.g., capacitors, resistors, etc., are outside the scope of this test method. Furthermore, this test method is only applicable for handheld products applications where cyclic bending due to repeated key-press operations is a concern. The size of surface mount device is limited to 15 mm x 15 mm maximum.
Correlation between test and field conditions is not yet fully established. Consequently, the test procedure is presently more appropriate for relative SMT IC performance than for use as a pass/fail criterion. However, to do comparisons care must be taken to have the same test variables used, such as SMT IC configuration and size.
This publication assumes a surface mount device such as BGAs, LGAs (excluding sockets and connectors), TSOP, and CSPs. Discrete SMT devices, e.g., capacitors, resistors, etc., are outside the scope of this test method. Furthermore, this test method is only applicable for handheld products applications where cyclic bending due to repeated key-press operations is a concern. The size of surface mount device is limited to 15 mm x 15 mm maximum.
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JEDEC JESD22B113A
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| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T16:31:00Z | |
| date available | 2017-09-04T16:31:00Z | |
| date copyright | 09/01/2012 | |
| date issued | 2012 | |
| identifier other | BPEKZEAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std;quein=autho123393FD081DAC4/handle/yse/94401 | |
| description abstract | The Board Level Cyclic Bend Test Method is intended to evaluate and compare the performance of SMT ICs in an accelerated test environment for handheld electronic products applications. The purpose is to standardize the test methodology to provide a reproducible performance assessment of SMT ICs while duplicating the failure modes normally observed during product level test. This is not a SMT IC qualification test and is not meant to replace any product level test that may be needed to qualify a specific product and assembly. Correlation between test and field conditions is not yet fully established. Consequently, the test procedure is presently more appropriate for relative SMT IC performance than for use as a pass/fail criterion. However, to do comparisons care must be taken to have the same test variables used, such as SMT IC configuration and size. This publication assumes a surface mount device such as BGAs, LGAs (excluding sockets and connectors), TSOP, and CSPs. Discrete SMT devices, e.g., capacitors, resistors, etc., are outside the scope of this test method. Furthermore, this test method is only applicable for handheld products applications where cyclic bending due to repeated key-press operations is a concern. The size of surface mount device is limited to 15 mm x 15 mm maximum. | |
| language | English | |
| title | JEDEC JESD22B113A | num |
| title | Board Level Cyclic Bend Test Method for Interconnect Reliability Characterization of SMT ICs for Handheld Electronic Products | en |
| type | standard | |
| page | 22 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;2012 | |
| contenttype | fulltext |