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MIL-STD-2217 CHG NOTICE 1

MEMORY LOADER/VERIFIER MULTIPLEX BUS INTERFACE WITH AVIONIC SYSTEMS, REQUIREMENTS FOR

Organization:
NAVY - AS - Naval Air Systems Command
Year: 1993

Abstract: The Memory Loader/Verifier (MLV) will provide the means for loading and verifying avionics memories in military aircraft utilizing a multiplex bus interface.
New or modified memory data will first be processed by designated facilities for each avionic system. It will then be transmitted to each user and transferred to the MLV Memory Storage Device (MSD) at the Intermediate Maintenance Activity (IMA). The MSD in each MLV will then contain a completely updated record of all memory data to be loaded into the avionic memories.
The MLV, using the interfaces defined herein, will be utilized to reprogram all applicable systems aboard an aircraft at the organizational maintenance level (O-Level). It will load the new data into the memories of the appropriate avionics systems and verify that the memories have been correctly loaded where possible.
Two types (Type I and Type II) of aircraft interface connections are called out in this document. The two types are defined in order to allow for compliance with contractual requirements and physical constraints that differ between aircraft. The Type I interface is defined to accommodate the physical constraints of existing aircraft and if within contractual constraints may be used for all existing aircraft. The Type II interface shall be used for all new designs and may be used for any existing aircraft. Individual Interface Control Documents (ICD) for each aircraft will define user definable items such as specific bus connections. These ICDs shall not repeat items specified herein.
This standard shall be used for the development of MLV interfaces for all avionic equipment to be reprogrammed via MIL-STD-1553 type bus interfaces. Individual Interface Control Documents (ICDs) for each unit, to specify user definable items described herein, will be required to allow Memory Storage Device preparation. These ICDs shall comply with this document and shall not repeat items specified herein.
This standard is applicable to all equipment reprogrammable at "O" level via a MIL-STD-1553 multiplex data bus and all new aircraft or aircraft modified to incorporate avionic equipment in conformance to this standard. All new equipment designs designated as Remote Terminals shall utilize the protocol defined in Appendix B of this document. All new equipment designs designated as Bus Controller shall utilize the protocol of Appendix C of this standard until the MLV is allocated the Bus Controller function and then shall utilize the protocol of Appendix B of this document. Equipment previously designed for which reprogramming capability is being added shall utilize the protocol of Appendix B or C of this document. Only equipment that is currently reprogrammable in the fleet via a MIL-STD-1553 multiplex data bus (or modifications to those equipments) shall utilize the protocol of Appendices D, E, F, G or H. All reprogrammable equipment not committed to production prior to the date of this document shall use at least one reprogramming enable discrete.
URI: http://yse.yabesh.ir/std;query=anid=47037D83081DAC4210946D6E273C9FCD/handle/yse/217991
Subject: Asynchronous
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  • NAVY - AS - Naval Air Systems Command
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    MIL-STD-2217 CHG NOTICE 1

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contributor authorNAVY - AS - Naval Air Systems Command
date accessioned2017-09-04T18:36:01Z
date available2017-09-04T18:36:01Z
date copyright05/28/1993
date issued1993
identifier otherJKDXDAAAAAAAAAAA.pdf
identifier urihttp://yse.yabesh.ir/std;query=anid=47037D83081DAC4210946D6E273C9FCD/handle/yse/217991
description abstractThe Memory Loader/Verifier (MLV) will provide the means for loading and verifying avionics memories in military aircraft utilizing a multiplex bus interface.
New or modified memory data will first be processed by designated facilities for each avionic system. It will then be transmitted to each user and transferred to the MLV Memory Storage Device (MSD) at the Intermediate Maintenance Activity (IMA). The MSD in each MLV will then contain a completely updated record of all memory data to be loaded into the avionic memories.
The MLV, using the interfaces defined herein, will be utilized to reprogram all applicable systems aboard an aircraft at the organizational maintenance level (O-Level). It will load the new data into the memories of the appropriate avionics systems and verify that the memories have been correctly loaded where possible.
Two types (Type I and Type II) of aircraft interface connections are called out in this document. The two types are defined in order to allow for compliance with contractual requirements and physical constraints that differ between aircraft. The Type I interface is defined to accommodate the physical constraints of existing aircraft and if within contractual constraints may be used for all existing aircraft. The Type II interface shall be used for all new designs and may be used for any existing aircraft. Individual Interface Control Documents (ICD) for each aircraft will define user definable items such as specific bus connections. These ICDs shall not repeat items specified herein.
This standard shall be used for the development of MLV interfaces for all avionic equipment to be reprogrammed via MIL-STD-1553 type bus interfaces. Individual Interface Control Documents (ICDs) for each unit, to specify user definable items described herein, will be required to allow Memory Storage Device preparation. These ICDs shall comply with this document and shall not repeat items specified herein.
This standard is applicable to all equipment reprogrammable at "O" level via a MIL-STD-1553 multiplex data bus and all new aircraft or aircraft modified to incorporate avionic equipment in conformance to this standard. All new equipment designs designated as Remote Terminals shall utilize the protocol defined in Appendix B of this document. All new equipment designs designated as Bus Controller shall utilize the protocol of Appendix C of this standard until the MLV is allocated the Bus Controller function and then shall utilize the protocol of Appendix B of this document. Equipment previously designed for which reprogramming capability is being added shall utilize the protocol of Appendix B or C of this document. Only equipment that is currently reprogrammable in the fleet via a MIL-STD-1553 multiplex data bus (or modifications to those equipments) shall utilize the protocol of Appendices D, E, F, G or H. All reprogrammable equipment not committed to production prior to the date of this document shall use at least one reprogramming enable discrete.
languageEnglish
titleMIL-STD-2217 CHG NOTICE 1num
titleMEMORY LOADER/VERIFIER MULTIPLEX BUS INTERFACE WITH AVIONIC SYSTEMS, REQUIREMENTS FORen
typestandard
page223
statusActive
treeNAVY - AS - Naval Air Systems Command:;1993
contenttypefulltext
subject keywordsAsynchronous
subject keywordsBit rate
subject keywordsBootstrap loading
subject keywordsBus controller (BC)
subject keywordsData bus
subject keywordsData word
subject keywordsLibrary file
subject keywordsLockup table
subject keywordsMemory file
subject keywordsMessage
subject keywordsPulse code modulation
subject keywordsRemote terminal (RT)
subject keywordsReprogramming data
subject keywordsStatus word
subject keywordsTime division multiplexing (TDM)
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