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JEDEC JESD8-2

Standard for Operating Voltages and Interface Levels for Low Voltage Emitter-Coupled Logic (ECL) Integrated Circuits

Organization:
JEDEC - Solid State Technology Association
Year: 1993

Abstract: This Addendum No. 2 to JEDEC Standard No. 8 provides standard operating voltage and interface levels that can be used by designers and application engineers as they develop and introduce new products. Covers the ECL logic family designated 300K ECL. The 300K ECL family is Voltage and Temperature Compensated, with I/O interface levels compatible with the existing 100K ECL and 101K ECl families.
URI: http://yse.yabesh.ir/std;query=autho1513AF679D40AC4/handle/yse/132559
Subject: ECL - Emitter-Coupled Logic
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    JEDEC JESD8-2

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contributor authorJEDEC - Solid State Technology Association
date accessioned2017-09-04T17:09:02Z
date available2017-09-04T17:09:02Z
date copyright01/01/1993
date issued1993
identifier otherYLYUCAAAAAAAAAAA.pdf
identifier urihttp://yse.yabesh.ir/std;query=autho1513AF679D40AC4/handle/yse/132559
description abstractThis Addendum No. 2 to JEDEC Standard No. 8 provides standard operating voltage and interface levels that can be used by designers and application engineers as they develop and introduce new products. Covers the ECL logic family designated 300K ECL. The 300K ECL family is Voltage and Temperature Compensated, with I/O interface levels compatible with the existing 100K ECL and 101K ECl families.
languageEnglish
titleJEDEC JESD8-2num
titleStandard for Operating Voltages and Interface Levels for Low Voltage Emitter-Coupled Logic (ECL) Integrated Circuitsen
typestandard
page7
statusActive
treeJEDEC - Solid State Technology Association:;1993
contenttypefulltext
subject keywordsECL - Emitter-Coupled Logic
subject keywordsEmitter-Coupled Logic - ECL
subject keywordsIntegrated Circuits
subject keywordsInterface Levels - ECL
subject keywordsOperating Voltages - ECL
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