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Design and Assembly Process Implementation for Flip Chip and Die Size Components

contributor authorIPC - Association Connecting Electronics Industries
date accessioned2017-09-04T16:55:07Z
date available2017-09-04T16:55:07Z
date copyright02/01/2009
date issued2009
identifier otherXAQOLCAAAAAAAAAA.pdf
identifier urihttp://yse.yabesh.ir/std;query=autho18267D83FCDCAC6/handle/yse/118650
description abstractThis document describes the design and assembly challenges for implementing flip chip technology in a direct chip attach (DCA) assembly. The effect of bare die or die size components in a flip chip format has an impact on current component characteristics and dictates the appropriate assembly methodology. The focus on the information contained herein is on design, assembly methodology, critical inspection, repair, and reliability issues associated with flip chip, and die size package technologies (including wafer level BGA).
Purpose The target audiences for this document are managers, design and process engineers, and operators and technicians who deal with the electronic assembly, inspection, and repair processes. The intent is to provide useful and practical information to those who are mounting bare die or die size components in a DCA assembly or those who are considering flip chip process implementation.
languageEnglish
titleIPC 7094num
titleDesign and Assembly Process Implementation for Flip Chip and Die Size Componentsen
typestandard
page88
statusActive
treeIPC - Association Connecting Electronics Industries:;2009
contenttypefulltext


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