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JEDEC JESD75-5
SON/QFN Package Pinouts Standardized for 1-, 2-, and 3-Bit Logic Functions
Organization:
JEDEC - Solid State Technology Association
Year: 2004
Abstract: This standard defines device pinout for 1-, 2- and 3-bit wide logic functions. This pinout specifically applies to the conversion of Dual-Inline-Packaged (DIP) 1-, 2- and 3-bit logic devices to SON/QFN packaged 1-, 2- and 3-bit logic devices. The purpose of this document is to provide a pinout standard for 1-, 2- and 3-bit logic devices offered in 5-, 6- or 8-land SON/QFN packages for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.
Subject: 1-Bit
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| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T15:43:28Z | |
| date available | 2017-09-04T15:43:28Z | |
| date copyright | 07/01/2004 | |
| date issued | 2004 | |
| identifier other | PMDQFBAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std;query=autho4703177/handle/yse/45734 | |
| description abstract | This standard defines device pinout for 1-, 2- and 3-bit wide logic functions. This pinout specifically applies to the conversion of Dual-Inline-Packaged (DIP) 1-, 2- and 3-bit logic devices to SON/QFN packaged 1-, 2- and 3-bit logic devices. The purpose of this document is to provide a pinout standard for 1-, 2- and 3-bit logic devices offered in 5-, 6- or 8-land SON/QFN packages for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. | |
| language | English | |
| title | JEDEC JESD75-5 | num |
| title | SON/QFN Package Pinouts Standardized for 1-, 2-, and 3-Bit Logic Functions | en |
| type | standard | |
| page | 13 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;2004 | |
| contenttype | fulltext | |
| subject keywords | 1-Bit | |
| subject keywords | 2-Bit | |
| subject keywords | 3-Bit | |
| subject keywords | PACKAGE PINOUTS | |
| subject keywords | QFN | |
| subject keywords | SON |