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IEEE Standard for the Functional Verification Language e

IEEE Std 1647-2019 (Revision of IEEE Std 1647-2016)

Organization:
IEEE - The Institute of Electrical and Electronics Engineers, Inc.
Year: 2019

Abstract: The e functional verification language is an application-specific programming language, aimed at automating the task of verifying a hardware or software design with respect to its specification. Verification environments written in e provide a model of the environment in which the design is expected to function, including the kinds of erroneous conditions the design needs to withstand. A typical verification environment is capable of generating user-controlled test inputs with statistically interesting characteristics. Such an environment can check the validity of the design responses. Functional coverage metrics are used to control the verification effort and gauge the quality of the design. e verification environments can be used throughout the design cycle, from a high-level architectural model to a fully realized system. A definition of the e language syntax and semantics and how tool developers and verification engineers should use them are contained in this standard.
URI: http://yse.yabesh.ir/std;query=authoF2377D8669B749A/handle/yse/276482
Subject: dynamic verification
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    IEEE Standard for the Functional Verification Language e

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contributor authorIEEE - The Institute of Electrical and Electronics Engineers, Inc.
date accessioned2020-06-18T16:56:22Z
date available2020-06-18T16:56:22Z
date issued2019
identifier isbn978-1-5044-5824
identifier other08793253.pdf
identifier urihttp://yse.yabesh.ir/std;query=authoF2377D8669B749A/handle/yse/276482
description abstractThe e functional verification language is an application-specific programming language, aimed at automating the task of verifying a hardware or software design with respect to its specification. Verification environments written in e provide a model of the environment in which the design is expected to function, including the kinds of erroneous conditions the design needs to withstand. A typical verification environment is capable of generating user-controlled test inputs with statistically interesting characteristics. Such an environment can check the validity of the design responses. Functional coverage metrics are used to control the verification effort and gauge the quality of the design. e verification environments can be used throughout the design cycle, from a high-level architectural model to a fully realized system. A definition of the e language syntax and semantics and how tool developers and verification engineers should use them are contained in this standard.
languageEnglish
titleIEEE Standard for the Functional Verification Language een
titleIEEE Std 1647-2019 (Revision of IEEE Std 1647-2016)num
typeStandard
page622
treeIEEE - The Institute of Electrical and Electronics Engineers, Inc.:;2019
contenttypeFulltext
subject keywordsdynamic verification
subject keywordsconcurrent programming
subject keywordsIEEE 1647
subject keywordsconstraint
subject keywordssimulation
subject keywordsfunctional verification
subject keywordsfunctional coverage
subject keywordstemporal logic
subject keywordstest generation
subject keywordsassertion
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