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Guide for Standard Probe Pad Sizes and Layouts for Wafer-Level Electrical Testing

contributor authorJEDEC - Solid State Technology Association
date accessioned2017-09-04T16:49:49Z
date available2017-09-04T16:49:49Z
date copyright35370
date issued1996
identifier otherWMJSCAAAAAAAAAAA.pdf
identifier urihttp://yse.yabesh.ir/std;quessionid=2A40ear/handle/yse/113441
description abstractThis guide was developed to expedite inter-laboratory experiments used to evaluate or develop standard test methods that involve test-structure measurements or tests. It also facilitates, generally, any electrical tests that require wafer-probe card to make electrical contact to test structures. Widespread use of this guide will afford the efficient and cost-effective use of water-probe test stations because of the need for fewer probe cards and probe-card changes to accommodate the various test structures that may need to be tested. 
languageEnglish
titleJEDEC JEP128num
titleGuide for Standard Probe Pad Sizes and Layouts for Wafer-Level Electrical Testingen
typestandard
page11
statusActive
treeJEDEC - Solid State Technology Association:;1996
contenttypefulltext
subject keywordsProbe - Pad Sizes and Layouts
subject keywordsWafer Level Electrical Testing


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