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JEDEC JEP128
Guide for Standard Probe Pad Sizes and Layouts for Wafer-Level Electrical Testing
Organization:
JEDEC - Solid State Technology Association
Year: 1996
Abstract: This guide was developed to expedite inter-laboratory experiments used to evaluate or develop standard test methods that involve test-structure measurements or tests. It also facilitates, generally, any electrical tests that require wafer-probe card to make electrical contact to test structures. Widespread use of this guide will afford the efficient and cost-effective use of water-probe test stations because of the need for fewer probe cards and probe-card changes to accommodate the various test structures that may need to be tested.
Subject: Probe - Pad Sizes and Layouts
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| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T16:49:49Z | |
| date available | 2017-09-04T16:49:49Z | |
| date copyright | 35370 | |
| date issued | 1996 | |
| identifier other | WMJSCAAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std;quessionid=2A40ear/handle/yse/113441 | |
| description abstract | This guide was developed to expedite inter-laboratory experiments used to evaluate or develop standard test methods that involve test-structure measurements or tests. It also facilitates, generally, any electrical tests that require wafer-probe card to make electrical contact to test structures. Widespread use of this guide will afford the efficient and cost-effective use of water-probe test stations because of the need for fewer probe cards and probe-card changes to accommodate the various test structures that may need to be tested. | |
| language | English | |
| title | JEDEC JEP128 | num |
| title | Guide for Standard Probe Pad Sizes and Layouts for Wafer-Level Electrical Testing | en |
| type | standard | |
| page | 11 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;1996 | |
| contenttype | fulltext | |
| subject keywords | Probe - Pad Sizes and Layouts | |
| subject keywords | Wafer Level Electrical Testing |