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JEDEC JESD89-1A
Test Method for Real-Time Soft Error Rate
| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T17:12:46Z | |
| date available | 2017-09-04T17:12:46Z | |
| date copyright | 39356 | |
| date issued | 2007 | |
| identifier other | YWOFBCAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std;quessionid=2A40ear/handle/yse/136346 | |
| description abstract | This test is used to determine the Soft Error Rate (SER) of solid state volatile memory arrays and bistable logic elements (e.g. flip-flops) for errors which require no more than re-reading or re-writing to correct and as used in terrestrial environments. It simulates the operating condition of the device and is used for qualification, characterization, or reliability monitoring. This test is intended for execution in ambient conditions without the artificial introduction of radiation sources. | |
| language | English | |
| title | JEDEC JESD89-1A | num |
| title | Test Method for Real-Time Soft Error Rate | en |
| type | standard | |
| page | 12 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;2007 | |
| contenttype | fulltext | |
| subject keywords | Error Rate | |
| subject keywords | Life Test | |
| subject keywords | Real-Time | |
| subject keywords | SER | |
| subject keywords | System | |
| subject keywords | Test Method - Soft Error Rate |
