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JEDEC JESD28-A

Procedure for Measuring N-Channel MOSFET Hot-Carrier-Induced Degradation under DC Stress

Organization:
JEDEC - Solid State Technology Association
Year: 2001

Abstract: This document describes an accelerated test for measuring the hot-carrier-induced degradation of a single n-channel MOSFET using dc bias. The purpose of this document is to specify a minimum set of measurements so that valid comparisons can be made between different technologies, IC processes, and process variations in a simple, consistent and controlled way. The measurements specified should be viewed as a starting point in the characterization and benchmarking of the transistor manufacturing process.
URI: http://yse.yabesh.ir/std;query=autho162sAF679D/handle/yse/137471
Subject: DC Stress
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contributor authorJEDEC - Solid State Technology Association
date accessioned2017-09-04T17:13:59Z
date available2017-09-04T17:13:59Z
date copyright37226
date issued2001
identifier otherYZPEUAAAAAAAAAAA.pdf
identifier urihttp://yse.yabesh.ir/std;query=autho162sAF679D/handle/yse/137471
description abstractThis document describes an accelerated test for measuring the hot-carrier-induced degradation of a single n-channel MOSFET using dc bias. The purpose of this document is to specify a minimum set of measurements so that valid comparisons can be made between different technologies, IC processes, and process variations in a simple, consistent and controlled way. The measurements specified should be viewed as a starting point in the characterization and benchmarking of the transistor manufacturing process.
languageEnglish
titleJEDEC JESD28-Anum
titleProcedure for Measuring N-Channel MOSFET Hot-Carrier-Induced Degradation under DC Stressen
typestandard
page20
statusActive
treeJEDEC - Solid State Technology Association:;2001
contenttypefulltext
subject keywordsDC Stress
subject keywordsHot Carrier Induced Degradation
subject keywordsN-Channel MOSFET
subject keywordsTest Method - Hot Carrier
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