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JEDEC JESD8-24

POD12 ‐ 1.2 V PSEUDO OPEN DRAIN INTERFACE

Organization:
JEDEC - Solid State Technology Association
Year: 2011

Abstract: This document defines the 1.2 V Pseudo Open Drain Interface family of interface standards, POD12, which are generally expected to be implemented with differential amp-based input buffers that, when in singleended mode, employ an externally supplied (or internal supplied) reference voltage controlled trip-point.
Although this standard is named for the nominal value of VDDQ to be used, it is the input trip-point value that provides for inter operability of POD12 compliant devices. Physics dictates variations in output driver characteristics and termination values in different interconnect network topologies. Drivers and terminators appropriate in a point-to-point interconnect scheme are not necessarily suitable in a multi-drop bus application. Multiple Classes of POD12 are expected to reside within the family of POD12 interfaces in order to accommodate various device and market applications. The various classes standardized within the context of POD12 are documented in the annex of this document (e.g., POD12/Class A, POD12/Class B, POD12/Class C, etc.)
In all cases, drivers and terminators are expected to produce a roughly symmetric swing about the input trippoint of POD12 receivers. Unlike the signals on other interfaces, such as HSTL, that are designed to produce signals that swing symmetrically about VDDQ/2, the signals on a POD12 interconnect line are not generally expected to pull to VSS. POD12 input buffers are generally expected to be supported by pull-uponly parallel input termination. POD12 output drivers are therefore expected to demonstrate an asymmetric output drive impedance. In point-to-point applications, for example, if the output drivers were expected to demonstrate a nominal 60 ohm pull-up drive impedance then the pull-down drivers would be expected to produce a 40 ohm pull-down drive impedance.
The core of this standard defines the dc and ac single-ended and differential operating conditions for POD12 input buffers as well as the terms and definitions necessary to describe the characteristics and behavior of output drivers. Clause 2 documents the subset of values common to all Classes of POD12 and documents specification items left to definition within a specific Class. The values specific to each particular class of POD12 are found in the annex. (Note it does not follow that all specification values defined in a given Class are necessarily different from the matching parameter in other Class within POD12. Multiple Classes may reuse a given specification value if appropriate to the Class requirements.)
Inasmuch as additional classes may be added to this standard at the will of the authorizing committee and the JEDEC Board of Directors, the reader is advised to check the JEDEC website (http://www.jedec.org) for the latest release of the standard.
URI: http://yse.yabesh.ir/std;quessionid=2A40ear/handle/yse/76134
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contributor authorJEDEC - Solid State Technology Association
date accessioned2017-09-04T16:12:52Z
date available2017-09-04T16:12:52Z
date copyright08/01/2011
date issued2011
identifier otherBJTENEAAAAAAAAAA.pdf
identifier urihttp://yse.yabesh.ir/std;quessionid=2A40ear/handle/yse/76134
description abstractThis document defines the 1.2 V Pseudo Open Drain Interface family of interface standards, POD12, which are generally expected to be implemented with differential amp-based input buffers that, when in singleended mode, employ an externally supplied (or internal supplied) reference voltage controlled trip-point.
Although this standard is named for the nominal value of VDDQ to be used, it is the input trip-point value that provides for inter operability of POD12 compliant devices. Physics dictates variations in output driver characteristics and termination values in different interconnect network topologies. Drivers and terminators appropriate in a point-to-point interconnect scheme are not necessarily suitable in a multi-drop bus application. Multiple Classes of POD12 are expected to reside within the family of POD12 interfaces in order to accommodate various device and market applications. The various classes standardized within the context of POD12 are documented in the annex of this document (e.g., POD12/Class A, POD12/Class B, POD12/Class C, etc.)
In all cases, drivers and terminators are expected to produce a roughly symmetric swing about the input trippoint of POD12 receivers. Unlike the signals on other interfaces, such as HSTL, that are designed to produce signals that swing symmetrically about VDDQ/2, the signals on a POD12 interconnect line are not generally expected to pull to VSS. POD12 input buffers are generally expected to be supported by pull-uponly parallel input termination. POD12 output drivers are therefore expected to demonstrate an asymmetric output drive impedance. In point-to-point applications, for example, if the output drivers were expected to demonstrate a nominal 60 ohm pull-up drive impedance then the pull-down drivers would be expected to produce a 40 ohm pull-down drive impedance.
The core of this standard defines the dc and ac single-ended and differential operating conditions for POD12 input buffers as well as the terms and definitions necessary to describe the characteristics and behavior of output drivers. Clause 2 documents the subset of values common to all Classes of POD12 and documents specification items left to definition within a specific Class. The values specific to each particular class of POD12 are found in the annex. (Note it does not follow that all specification values defined in a given Class are necessarily different from the matching parameter in other Class within POD12. Multiple Classes may reuse a given specification value if appropriate to the Class requirements.)
Inasmuch as additional classes may be added to this standard at the will of the authorizing committee and the JEDEC Board of Directors, the reader is advised to check the JEDEC website (http://www.jedec.org) for the latest release of the standard.
languageEnglish
titleJEDEC JESD8-24num
titlePOD12 ‐ 1.2 V PSEUDO OPEN DRAIN INTERFACEen
typestandard
page16
statusActive
treeJEDEC - Solid State Technology Association:;2011
contenttypefulltext
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