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JEDEC JESD35-1

General Guidelines for Designing Test Structures for the Wafer-Level Testing of Thin Dielectrics - Addendum No. 1 to JESD35

Organization:
JEDEC - Solid State Technology Association
Year: 1995

Abstract: This addendum expands the usefulness of the Standard 35 (JESD35) by detailing the various sources of measurement error that could effect the test results obtained by the ramped tests described in JESD35. Each source of error is described and its implications on test structure design is noted. This addendum can be used as a guide when designing test structures for the qualification and characterization of thin oxide reliability, specifically, by implementing accelerated voltage or current ramp tests.
URI: http://yse.yabesh.ir/std;quessionid=2A40ear/handle/yse/87715
Subject: Test Structure - Thin Dielectrics
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contributor authorJEDEC - Solid State Technology Association
date accessioned2017-09-04T16:24:21Z
date available2017-09-04T16:24:21Z
date copyright09/01/1995
date issued1995
identifier otherTVCLCAAAAAAAAAAA.pdf
identifier urihttp://yse.yabesh.ir/std;quessionid=2A40ear/handle/yse/87715
description abstractThis addendum expands the usefulness of the Standard 35 (JESD35) by detailing the various sources of measurement error that could effect the test results obtained by the ramped tests described in JESD35. Each source of error is described and its implications on test structure design is noted. This addendum can be used as a guide when designing test structures for the qualification and characterization of thin oxide reliability, specifically, by implementing accelerated voltage or current ramp tests.
languageEnglish
titleJEDEC JESD35-1num
titleGeneral Guidelines for Designing Test Structures for the Wafer-Level Testing of Thin Dielectrics - Addendum No. 1 to JESD35en
typestandard
page26
statusActive
treeJEDEC - Solid State Technology Association:;1995
contenttypefulltext
subject keywordsTest Structure - Thin Dielectrics
subject keywordsThin Dielectrics
subject keywordsWafer-Level Testing
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