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IEEE 1364
Standard Verilog Hardware Description Language - IEEE Computer Society Document
Year: 2005
Abstract: Verilog is a hardware description language (HDL) that was standardized as IEEE Std 1364™-1995 and first revised as IEEE Std 1364-2001. This revision corrects and clarifies features ambiguously described in the 1995 and 2001 editions. It also resolves incompatibilities and inconsistencies of IEEE 1364-2001 with IEEE Std 1800™-2005.
The intent of this standard is to serve as a complete specification of the Verilog HDL. This standard contains the following:— The formal syntax and semantics of all Verilog HDL constructs— The formal syntax and semantics of standard delay format (SDF) constructs— Simulation system tasks and functions, such as text output display commands— Compiler directives, such as text substitution macros and simulation time scaling— The programming language interface (PLI) binding mechanism— The formal syntax and semantics of the Verilog procedural interface (VPI)— Informative usage examples— Informative delay model for SDF— The VPI header file
The intent of this standard is to serve as a complete specification of the Verilog HDL. This standard contains the following:— The formal syntax and semantics of all Verilog HDL constructs— The formal syntax and semantics of standard delay format (SDF) constructs— Simulation system tasks and functions, such as text output display commands— Compiler directives, such as text substitution macros and simulation time scaling— The programming language interface (PLI) binding mechanism— The formal syntax and semantics of the Verilog procedural interface (VPI)— Informative usage examples— Informative delay model for SDF— The VPI header file
Subject: computer
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| contributor author | IEEE - The Institute of Electrical and Electronics Engineers, Inc. | |
| date accessioned | 2017-09-04T17:19:57Z | |
| date available | 2017-09-04T17:19:57Z | |
| date copyright | 01/01/2005 | |
| date issued | 2005 | |
| identifier other | ZOUAJBAAAAAAAAAA.pdf | |
| identifier uri | https://yse.yabesh.ir/std/handle/yse/143172 | |
| description abstract | Verilog is a hardware description language (HDL) that was standardized as IEEE Std 1364™-1995 and first revised as IEEE Std 1364-2001. This revision corrects and clarifies features ambiguously described in the 1995 and 2001 editions. It also resolves incompatibilities and inconsistencies of IEEE 1364-2001 with IEEE Std 1800™-2005. The intent of this standard is to serve as a complete specification of the Verilog HDL. This standard contains the following:— The formal syntax and semantics of all Verilog HDL constructs— The formal syntax and semantics of standard delay format (SDF) constructs— Simulation system tasks and functions, such as text output display commands— Compiler directives, such as text substitution macros and simulation time scaling— The programming language interface (PLI) binding mechanism— The formal syntax and semantics of the Verilog procedural interface (VPI)— Informative usage examples— Informative delay model for SDF— The VPI header file | |
| language | English | |
| title | IEEE 1364 | num |
| title | Standard Verilog Hardware Description Language - IEEE Computer Society Document | en |
| type | standard | |
| page | 590 | |
| status | Active | |
| tree | IEEE - The Institute of Electrical and Electronics Engineers, Inc.:;2005 | |
| contenttype | fulltext | |
| subject keywords | computer | |
| subject keywords | computer languages | |
| subject keywords | digital systems | |
| subject keywords | electronic systems | |
| subject keywords | hardware | |
| subject keywords | hardware description languages | |
| subject keywords | hardware design | |
| subject keywords | HDL | |
| subject keywords | PLI | |
| subject keywords | programming language interface | |
| subject keywords | Verilog | |
| subject keywords | Verilog HDL | |
| subject keywords | Verilog PLI |