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IEEE 1364
Behavioural languages - Part 4: Verilog hardware description language - IEEE Computer Society Document
Year: 2004
Abstract: Objectives of this standard
The intent of this standard is to serve as a complete specification of the Verilog ® Hardware Description Language (HDL). This document contains
— The formal syntax and semantics of all Verilog HDL constructs
— The formal syntax and semantics of Standard Delay Format (SDF) constructs
— Simulation system tasks and functions, such as text output display commands
— Compiler directives, such as text substitution macros and simulation time scaling
— The Programming Language Interface (PLI) binding mechanism
— The formal syntax and semantics of access routines, task/function routines, and Verilog procedural interface routines
— Informative usage examples
— Informative delay model for SDF
— Listings of header files for PLI
The intent of this standard is to serve as a complete specification of the Verilog ® Hardware Description Language (HDL). This document contains
— The formal syntax and semantics of all Verilog HDL constructs
— The formal syntax and semantics of Standard Delay Format (SDF) constructs
— Simulation system tasks and functions, such as text output display commands
— Compiler directives, such as text substitution macros and simulation time scaling
— The Programming Language Interface (PLI) binding mechanism
— The formal syntax and semantics of access routines, task/function routines, and Verilog procedural interface routines
— Informative usage examples
— Informative delay model for SDF
— Listings of header files for PLI
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| contributor author | IEEE - The Institute of Electrical and Electronics Engineers, Inc. | |
| date accessioned | 2017-09-04T17:56:03Z | |
| date available | 2017-09-04T17:56:03Z | |
| date copyright | 38261 | |
| date issued | 2004 | |
| identifier other | FLKWGBAAAAAAAAAA.pdf | |
| identifier uri | https://yse.yabesh.ir/std/handle/yse/179186 | |
| description abstract | Objectives of this standard The intent of this standard is to serve as a complete specification of the Verilog ® Hardware Description Language (HDL). This document contains — The formal syntax and semantics of all Verilog HDL constructs — The formal syntax and semantics of Standard Delay Format (SDF) constructs — Simulation system tasks and functions, such as text output display commands — Compiler directives, such as text substitution macros and simulation time scaling — The Programming Language Interface (PLI) binding mechanism — The formal syntax and semantics of access routines, task/function routines, and Verilog procedural interface routines — Informative usage examples — Informative delay model for SDF — Listings of header files for PLI | |
| language | English | |
| title | IEEE 1364 | num |
| title | Behavioural languages - Part 4: Verilog hardware description language - IEEE Computer Society Document | en |
| type | standard | |
| page | 862 | |
| status | Active | |
| tree | IEEE - The Institute of Electrical and Electronics Engineers, Inc.:;2004 | |
| contenttype | fulltext |