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IEEE Standard for High-Speed Test Access Port and On-Chip Distribution Architecture

IEEE Std 1149.10-2017

contributor authorIEEE - The Institute of Electrical and Electronics Engineers, Inc.
date accessioned2018-07-30T06:05:27Z
date available2018-07-30T06:05:27Z
date copyrightJuly 28 2017
date issued2017
identifier isbnElectronic:978-1-5044-3995-4
identifier other7995164.pdf
identifier urihttps://yse.yabesh.ir/std/handle/yse/258389
description abstractCircuitry that may be built into an integrated circuit to assist in the test, maintenance, and support of assembled printed circuit boards, assembled multi-die packages, and the test of die internal circuits is defined in this standard. The circuitry includes a high-speed TAP (HSTAP) with a packet encoder/decoder and distribution architecture through which instructions and test data are communicated. The standard leverages the languages of IEEE Std 1149.1(TM) to describe and operate the on-chip circuits.
languageEnglish
titleIEEE Standard for High-Speed Test Access Port and On-Chip Distribution Architectureen
titleIEEE Std 1149.10-2017num
typestandard
page96
treeIEEE - The Institute of Electrical and Electronics Engineers, Inc.:;2017
contenttypefulltext
subject keywords3D-IC
subject keywordsBSDL
subject keywordsBoundary-Scan Description Language
subject keywordsHigh Speed JTAG
subject keywordsI2C
subject keywordsIEEE 1149.1(TM)
subject keywordsIEEE 1149.10(TM)
subject keywordsJTAG
subject keywordsPDL
subject keywordsProcedural Description Language
subject keywordsSERDES
subject keywordsSPI
subject keywordsdebug
subject keywordsintegrated circuit
subject keywordssystem level test
subject keywordswafer
subject keywordsBoundary conditions
subject keywordsIEEE Standards
subject keywordsIntegrated circuits
subject keywordsMaintenance engineering
subject keywordsPrinted circuits
subject keywordsSystem-on-chip
subject keywordsIEEE standards
subject keywordsdecoding
subject keywordsencoding
subject keywordshigh-speed integrated circuits
subject keywordsintegrated circuit packaging
subject keywordsintegrated circuit testing
subject keywordsHSTAP
subject keywordsIEEE Std 1149.10-2017
subject keywordsassembled multi-die packages
subject keywordsassembled printed circuit boards
subject keywordsdie internal circuits
subject keywordsdistribution architecture
subject keywordshigh-speed TAP
subject keywordsintegrated circuit
subject keywordson-chip circuits
subject keywordspacket encoder-decoder
identifier DOI10.1109/IEEESTD.2017.7995164


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