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IEEE Standard for High-Speed Test Access Port and On-Chip Distribution Architecture
IEEE Std 1149.10-2017
Year: 2017
Abstract: Circuitry that may be built into an integrated circuit to assist in the test, maintenance, and support of assembled printed circuit boards, assembled multi-die packages, and the test of die internal circuits is defined in this standard. The circuitry includes a high-speed TAP (HSTAP) with a packet encoder/decoder and distribution architecture through which instructions and test data are communicated. The standard leverages the languages of IEEE Std 1149.1(TM) to describe and operate the on-chip circuits.
Subject: 3D-IC
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IEEE Standard for High-Speed Test Access Port and On-Chip Distribution Architecture
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| contributor author | IEEE - The Institute of Electrical and Electronics Engineers, Inc. | |
| date accessioned | 2018-07-30T06:05:27Z | |
| date available | 2018-07-30T06:05:27Z | |
| date copyright | July 28 2017 | |
| date issued | 2017 | |
| identifier isbn | Electronic:978-1-5044-3995-4 | |
| identifier other | 7995164.pdf | |
| identifier uri | https://yse.yabesh.ir/std/handle/yse/258389 | |
| description abstract | Circuitry that may be built into an integrated circuit to assist in the test, maintenance, and support of assembled printed circuit boards, assembled multi-die packages, and the test of die internal circuits is defined in this standard. The circuitry includes a high-speed TAP (HSTAP) with a packet encoder/decoder and distribution architecture through which instructions and test data are communicated. The standard leverages the languages of IEEE Std 1149.1(TM) to describe and operate the on-chip circuits. | |
| language | English | |
| title | IEEE Standard for High-Speed Test Access Port and On-Chip Distribution Architecture | en |
| title | IEEE Std 1149.10-2017 | num |
| type | standard | |
| page | 96 | |
| tree | IEEE - The Institute of Electrical and Electronics Engineers, Inc.:;2017 | |
| contenttype | fulltext | |
| subject keywords | 3D-IC | |
| subject keywords | BSDL | |
| subject keywords | Boundary-Scan Description Language | |
| subject keywords | High Speed JTAG | |
| subject keywords | I2C | |
| subject keywords | IEEE 1149.1(TM) | |
| subject keywords | IEEE 1149.10(TM) | |
| subject keywords | JTAG | |
| subject keywords | PDL | |
| subject keywords | Procedural Description Language | |
| subject keywords | SERDES | |
| subject keywords | SPI | |
| subject keywords | debug | |
| subject keywords | integrated circuit | |
| subject keywords | system level test | |
| subject keywords | wafer | |
| subject keywords | Boundary conditions | |
| subject keywords | IEEE Standards | |
| subject keywords | Integrated circuits | |
| subject keywords | Maintenance engineering | |
| subject keywords | Printed circuits | |
| subject keywords | System-on-chip | |
| subject keywords | IEEE standards | |
| subject keywords | decoding | |
| subject keywords | encoding | |
| subject keywords | high-speed integrated circuits | |
| subject keywords | integrated circuit packaging | |
| subject keywords | integrated circuit testing | |
| subject keywords | HSTAP | |
| subject keywords | IEEE Std 1149.10-2017 | |
| subject keywords | assembled multi-die packages | |
| subject keywords | assembled printed circuit boards | |
| subject keywords | die internal circuits | |
| subject keywords | distribution architecture | |
| subject keywords | high-speed TAP | |
| subject keywords | integrated circuit | |
| subject keywords | on-chip circuits | |
| subject keywords | packet encoder-decoder | |
| identifier DOI | 10.1109/IEEESTD.2017.7995164 |