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IEEE Standard for Extensions to Standard Test Interface Language (STIL) for Semiconductor Design Environments
IEEE Std 1450.1-2025 (Revision of IEEE Std 1450.1-2005)
Year: 2025
IEEE - The Institute of Electrical and Electronics Engineers, Inc.
Abstract: An interface between digital test generation tools and test equipment is provided by Standard Test Interface Language (STIL). Extensions to the test interface language (contained in this standard) are defined that facilitate the use of the language in the design environment and facilitate the use of the language for large designs encompassing subdesigns with reusable patterns.
Subject: parameterized data
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IEEE Standard for Extensions to Standard Test Interface Language (STIL) for Semiconductor Design Environments
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| contributor author | IEEE - The Institute of Electrical and Electronics Engineers, Inc. | |
| date accessioned | 2025-09-30T23:08:35Z | |
| date available | 2025-09-30T23:08:35Z | |
| date copyright | 26 June 2025 | |
| date issued | 2025 | |
| identifier other | 11051143.pdf | |
| identifier uri | https://yse.yabesh.ir/std/handle/yse/348609 | |
| description abstract | An interface between digital test generation tools and test equipment is provided by Standard Test Interface Language (STIL). Extensions to the test interface language (contained in this standard) are defined that facilitate the use of the language in the design environment and facilitate the use of the language for large designs encompassing subdesigns with reusable patterns. | |
| language | English | |
| publisher | IEEE - The Institute of Electrical and Electronics Engineers, Inc. | |
| title | IEEE Standard for Extensions to Standard Test Interface Language (STIL) for Semiconductor Design Environments | en |
| title | IEEE Std 1450.1-2025 (Revision of IEEE Std 1450.1-2005) | num |
| type | standard | |
| page | 141 | |
| tree | IEEE - The Institute of Electrical and Electronics Engineers, Inc.:;2025 | |
| contenttype | fulltext | |
| subject keywords | parameterized data | |
| subject keywords | SoC | |
| subject keywords | pattern tiling | |
| subject keywords | advanced scan architecture | |
| subject keywords | environment | |
| subject keywords | IEEE 1450.1 | |
| subject keywords | core | |
| subject keywords | fail feedback | |
| subject keywords | pragma | |
| subject keywords | lockstep | |
| subject keywords | test protocol | |
| subject keywords | system on chip | |
| subject keywords | signal variable | |
| subject keywords | parallel patterns | |
| identifier DOI | 10.1109/IEEESTD.2025.11051143 |