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JEDEC JESD203
Standard Test Loads For Dual - Supply Level Translation Devices
Organization:
JEDEC - Solid State Technology Association
Year: 2005
Abstract: This standard defines ac test loads for dual-supply level translation devices. Uniform test loads enable easy comparison of electrical parameters of dual-supply level translation devices across functions, logic families and IC suppliers. This standard is only intended to apply to devices released subsequent to the publication of this document.
Subject: Dual-Supply Volatage
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| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T17:53:17Z | |
| date available | 2017-09-04T17:53:17Z | |
| date copyright | 38657 | |
| date issued | 2005 | |
| identifier other | FEDPIBAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std;quein=autho123393FD081DAC4/handle/yse/176470 | |
| description abstract | This standard defines ac test loads for dual-supply level translation devices. Uniform test loads enable easy comparison of electrical parameters of dual-supply level translation devices across functions, logic families and IC suppliers. This standard is only intended to apply to devices released subsequent to the publication of this document. | |
| language | English | |
| title | JEDEC JESD203 | num |
| title | Standard Test Loads For Dual - Supply Level Translation Devices | en |
| type | standard | |
| page | 10 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;2005 | |
| contenttype | fulltext | |
| subject keywords | Dual-Supply Volatage | |
| subject keywords | Test Loads | |
| subject keywords | Voltage Level Translation | |
| subject keywords | Voltage Logic Levels |