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JEDEC JESD64-A

Standard for Description of 2.5 V CMOS Logic Devices with 3.6 V CMOS Tolerant Inputs and Outputs

Organization:
JEDEC - Solid State Technology Association
Year: 2000

Abstract: The purpose is to provide a standard for 2.5 V nominal supply voltage logic devices for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This specification provides for compatibility between devices operating between either the Standard Range of 1.8 V to 2.7 V or the optional Extended Range of 1.65 V to 2.7 V supply voltages, as well as over-voltage tolerance with devices operating at 3.6 V.
URI: http://yse.yabesh.ir/std;query=autho1826AF679D/handle/yse/64436
Subject: CMOS Logic Devices
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    JEDEC JESD64-A

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contributor authorJEDEC - Solid State Technology Association
date accessioned2017-09-04T16:01:14Z
date available2017-09-04T16:01:14Z
date copyright36800
date issued2000
identifier otherRKNHCBAAAAAAAAAA.pdf
identifier urihttp://yse.yabesh.ir/std;query=autho1826AF679D/handle/yse/64436
description abstractThe purpose is to provide a standard for 2.5 V nominal supply voltage logic devices for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This specification provides for compatibility between devices operating between either the Standard Range of 1.8 V to 2.7 V or the optional Extended Range of 1.65 V to 2.7 V supply voltages, as well as over-voltage tolerance with devices operating at 3.6 V.
languageEnglish
titleJEDEC JESD64-Anum
titleStandard for Description of 2.5 V CMOS Logic Devices with 3.6 V CMOS Tolerant Inputs and Outputsen
typestandard
page11
statusActive
treeJEDEC - Solid State Technology Association:;2000
contenttypefulltext
subject keywordsCMOS Logic Devices
subject keywordsInput and Output - CMOS Tolerant
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