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JEDEC JESD90

A Procedure for Measuring P-Channel MOSFET Negative Bias Temperature Instabilities

Organization:
JEDEC - Solid State Technology Association
Year: 2004

Abstract: This document describes an accelerated stress and test methodology for measuring device parameter changes of a single p-channel MOSFET after Negative Bias Temperature Instability (NBTI) stress at dc bias conditions. This document gives a procedure to investigate NBTI stress in a symmetric voltage condition with the channel inverted (VGS < 0) and no channel conduction (VDS = 0).There can be NBTI degradation during channel conduction (VGS < 0, VDS < 0), however, this document does not cover this phenomena.
URI: http://yse.yabesh.ir/std;query=autho1826AF679D/handle/yse/66829
Subject: MOSFET
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contributor authorJEDEC - Solid State Technology Association
date accessioned2017-09-04T16:03:34Z
date available2017-09-04T16:03:34Z
date copyright38292
date issued2004
identifier otherRQVQGBAAAAAAAAAA.pdf
identifier urihttp://yse.yabesh.ir/std;query=autho1826AF679D/handle/yse/66829
description abstractThis document describes an accelerated stress and test methodology for measuring device parameter changes of a single p-channel MOSFET after Negative Bias Temperature Instability (NBTI) stress at dc bias conditions. This document gives a procedure to investigate NBTI stress in a symmetric voltage condition with the channel inverted (VGS < 0) and no channel conduction (VDS = 0).There can be NBTI degradation during channel conduction (VGS < 0, VDS < 0), however, this document does not cover this phenomena.
languageEnglish
titleJEDEC JESD90num
titleA Procedure for Measuring P-Channel MOSFET Negative Bias Temperature Instabilitiesen
typestandard
page20
statusActive
treeJEDEC - Solid State Technology Association:;2004
contenttypefulltext
subject keywordsMOSFET
subject keywordsNBTI
subject keywordsNegative Bias
subject keywordsP-Channel
subject keywordsPMOS
subject keywordsTemperature
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