درباره ما
IEEE 1850
Property Specification Language (PSL) - IEEE Computer Society
Year: 2010
Abstract: This standard defines the property specification language (PSL), which formally describes electronic system behavior. This standard specifies the syntax and semantics for PSL and also clarifies how PSL interfaces with various standard electronic system design languages.
Purpose
The purpose of this standard is to provide a well-defined language for formal specification of electronic system behavior, one that is compatible with multiple electronic system design languages, including IEEE Std 1076™ (VHDL®),1 IEEE Std 1364™ (Verilog®), IEEE Std 1800™ (SystemVerilog®), and IEEE Std 1666™ (SystemC®), to facilitate a common specification and verification flow for multi-language and mixed-language designs.
This standard creates an updated IEEE standard based upon IEEE Std 1850-2005. The updated standard will refine IEEE standard, addressing errata, minor technical issues, and proposed extensions specifically related to property reuse and improved simulation usability.
1Information on references can be found in Clause 2.
Purpose
The purpose of this standard is to provide a well-defined language for formal specification of electronic system behavior, one that is compatible with multiple electronic system design languages, including IEEE Std 1076™ (VHDL®),1 IEEE Std 1364™ (Verilog®), IEEE Std 1800™ (SystemVerilog®), and IEEE Std 1666™ (SystemC®), to facilitate a common specification and verification flow for multi-language and mixed-language designs.
This standard creates an updated IEEE standard based upon IEEE Std 1850-2005. The updated standard will refine IEEE standard, addressing errata, minor technical issues, and proposed extensions specifically related to property reuse and improved simulation usability.
1Information on references can be found in Clause 2.
Subject: ABV
Show full item record
| contributor author | IEEE - The Institute of Electrical and Electronics Engineers, Inc. | |
| date accessioned | 2017-09-04T16:40:31Z | |
| date available | 2017-09-04T16:40:31Z | |
| date copyright | 03/25/2010 | |
| date issued | 2010 | |
| identifier other | VNODSDAAAAAAAAAA.pdf | |
| identifier uri | https://yse.yabesh.ir/std/handle/yse/104077 | |
| description abstract | This standard defines the property specification language (PSL), which formally describes electronic system behavior. This standard specifies the syntax and semantics for PSL and also clarifies how PSL interfaces with various standard electronic system design languages. Purpose The purpose of this standard is to provide a well-defined language for formal specification of electronic system behavior, one that is compatible with multiple electronic system design languages, including IEEE Std 1076™ (VHDL®),1 IEEE Std 1364™ (Verilog®), IEEE Std 1800™ (SystemVerilog®), and IEEE Std 1666™ (SystemC®), to facilitate a common specification and verification flow for multi-language and mixed-language designs. This standard creates an updated IEEE standard based upon IEEE Std 1850-2005. The updated standard will refine IEEE standard, addressing errata, minor technical issues, and proposed extensions specifically related to property reuse and improved simulation usability. 1Information on references can be found in Clause 2. | |
| language | English | |
| title | IEEE 1850 | num |
| title | Property Specification Language (PSL) - IEEE Computer Society | en |
| type | standard | |
| page | 182 | |
| status | Active | |
| tree | IEEE - The Institute of Electrical and Electronics Engineers, Inc.:;2010 | |
| contenttype | fulltext | |
| subject keywords | ABV | |
| subject keywords | assertion | |
| subject keywords | assertion-based verification | |
| subject keywords | assumption | |
| subject keywords | cover | |
| subject keywords | model checking | |
| subject keywords | property | |
| subject keywords | PSL | |
| subject keywords | specification | |
| subject keywords | temporal logic | |
| subject keywords | verification |