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JEDEC JESD89A: Measurement and Reporting of Alpha Particle and Terrestrial Cosmic Ray-Induced Soft Errors in Semiconductor Devices
Abstract: This specification defines the standard requirements and procedures for terrestrial soft-error-rate (SER)testing of integrated circuits and reporting of results. Both real-time (unaccelerated) and acceleratedtesting ...
JEDEC JEP145: Guideline for Assessing the Current-Carrying Capability of the Leads in a Power Package System
Abstract: This publication is intended as a guideline to establish procedures, consideration and common practices that will allow a manufacturer, an application entity, a system designer and other interested parties to define current ...
JEDEC JEP158: 3D Chip Stack with Through-Silicon Vias (TSVS): Identifying, Evaluating and Understanding Reliability Interactions
Abstract: To increase device bandwidth, reduce power and shrink form factor, microelectronics manufacturers are implementing three dimensional (3D) chip stacking using through silicon vias (TSVs). Chip stacking with TSVs combines ...
JEDEC JESD8-23: Unified Wide Power Supply Voltage Range CMOS DC Interface Standard for Non-Terminated Digital Integrated Circuits
Abstract: This standard defines DC interface parameters and test conditions for a family of non-terminated CMOS digital circuits intended for use over a wide power supply voltage range. The standard bridges a number of existing JEDEC ...
JEDEC JESD82-17: Definition of the SSTUA32S868 and SSTUA32D868 Registered Buffer with Parity for 2R x 4 DDR2 RDIMM Applications
Abstract: This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUA32S868 and SSTUA32D868 registered buffer with parity test for DDR2 RDIMM applications.
JEDEC JESD38: Standard for Failure Analysis Report Format
Abstract: This standard is to promote unification of content and format of semiconductor device failure-analysis reports so that reports from diverse laboratories may be easily read, compared, and understood by customers. Additional ...
JEDEC JEP160: Long-Term Storage for Electronic Solid-State Wafers, Dice, and Devices
Abstract: This publication examines the LTS requirements of wafers, dice, and packaged solid-state devices. (Note: Packaging may include encapsulation, under-fill, over-mold, or other techniques to attach a die to the next level of ...
JEDEC JESD82-7A: Definition of the SSTU32864 1.8-V Configurable Registered Buffer for DDR2 RDIMM Applications
Abstract: This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTU32864 configurable registered buffer for DDR2 RDIMM applications. The purpose is ...
JEDEC JES2: Transistor, Gallium Arsenide Power Fet, Generic Specification
Abstract: Establishes guideline requirements and quality assurance provisions for gallium arsenide power field-effect transistors (FETs, also know as MESFETs) designed for use in high-reliability space application such as spacecraft ...
JEDEC JEP179: Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid State Surface- Mount Components
Abstract: The purpose of this document is to explain the meaning of SPD setting (JESD21 SPD section) for DDR2 SDRAM (JESD79-2) in normal and extended temperature operationy67.