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JEDEC - Solid State Technology Association: Recent submissions
Now showing items 341-360 of 369
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JEDEC JESD87
Abstract: This document describes design of test structures needed to assess the reliability of aluminum-copper, refractory metal barrier interconnect systems. This includes any metal interconnect system where a refractory metal ...Subject(s) : AlCu , Barrier Materials , Electromigration , EM , SIV , Stress-Induced-Voids , -
JEDEC JESD224
Abstract: The primary objective of this test standard is to specify the test cases for UFS device protocol conformance testing. This test standard provides test cases for checking the functions defined in the following target standard: ... -
JEDEC JESD51-4
Abstract: This guideline describes design requirements for wire bond type semiconductor chips to be used for thermal resistance listing of IC packages. This document provides specific guidelines for chip design but allows flexibility ...Subject(s) : Chip - Thermal Test , Thermal Test Chip , Wire Bond Type Chip , -
JEDEC JEP146A
Abstract: The intent of this document is to establish guidelines and provide examples by which customers can measure their suppliers based on mutually agreed upon objective criteria. These results can then be used to improve ... -
JEDEC JESD82-29A
Abstract: This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTE32882 registered buffer with parity for driving address and control nets on ... -
JEDEC JESD22-A119
Abstract: The test is applicable for evaluation, screening, monitoring, and/or qualification of all solid state devices. Low Temperature storage test is typically used to determine the effect of time and temperature, under storage ...Subject(s) : Low Temperature , Low Temperature Storage Life - Test Method , Storage Life , Test Method - Low Temperature Storage Life , -
JEDEC JESD51-2A
Abstract: This document outlines the environmental conditions necessary to ensure accuracy and repeatability for a standard junction-to-ambient thermal resistance measurement in natural convection.Subject(s) : Environmental Conditions , Natural Convection (Still Air) , Test Method - Environmental Conditions , -
JEDEC JESD223-1
Abstract: This document provides a comprehensive definition of the requirements for implementation of a UFS Host Controller, which supports the optional Unified Memory extension. -
JEDEC JESD6
Abstract: This standard gives a test method for measuring transistor capacitance using a three-terminal bridge which employs a guard-circuit that eliminates the effect of extraneous capacitance.Subject(s) : Capacitance - Transistor , Measurement - Small Value Transistor Capacitance , Small Values - Transistor Capacitance , Transistor - Capacitance , -
JEDEC JESD51-1
Abstract: The purpose of this test method is to define a standard Electrical Test Method (ETM) that can be used to determine the thermal characteristics of single integrated circuit devices housed in some form of electrical package. ...Subject(s) : Integrated Circuit Thermal Measurement , Single Semiconductor Device , Test Method - Electrical , Thermal Measurement - Integrated Circuit , -
JEDEC JESD75-6
Abstract: This standard defines device pinouts for 14-, 16-, 20-, and 24-lead logic functions. This pinout standard specifically applies to the conversion of DIP-packaged logic devices to PSO-N/PQFN packages logic devices. The purpose ...Subject(s) : Logic Functions , Pinout , PSO-N/PQFN , -
JEDEC JESD96A-1
Abstract: The normative information in this publication is intended to provide a technical design team to construct the interface on a FED and a BED such that they will operate correctly with each other (at the interface level), ...Subject(s) : Compliance , IEEE 802.11n , Interoperability , JESD96 , TRD , -
JEDEC JESD51-3
Abstract: This standard describes design requirements for a single layer, leaded surface mount integrated circuit package thermal test board. The standard describes board material and geometry requirements, minimum trace lenghts, ...Subject(s) : Design Requirements - Leaded Surface Mount , Thermal Test Board , -
JEDEC JESD79-3F
Abstract: This document defines the DDR3 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Specification is to define the minimum set of ... -
JEDEC JESD8-20A
Abstract: This standard defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedance, and the termination and calibration scheme for 1.5 V Pseudo Open Drain I/Os. The 1.5 V Pseudo Open Drain ...Subject(s) : 135.01 , DRAM , GDDR4 , GDDR5 , Interface , Memory , POD , POD15 , POD-15 , RAM , SGRAM , -
JEDEC JESD12-6
Abstract: This standard defines logic interface levels for CMOS, TTL, ECL, and BiCC inputs and outputs. This standard is intended to provide an industry-wide set of specifications, for Application Specific Integrated Circuit (ASIC) ...Subject(s) : BiCC , ECL , Interface Levels - 5 V Operation , Interface Standard - Semicustom ICs , Logic Interface Levels - CMOS , Semicustom Integrated Circuits , TTL , -
JEDEC JESD49A
Abstract: This standard was created to facilitate the procurement and use of high reliability semiconductor microcircuits or discrete devices provided in bare die form, commonly known as Known Good Die (KGD).Subject(s) : Bare Die , High Reliability , Known Good Die - KGD , -
JEDEC JESD84-B41
Abstract: This document provides a comprehensive definition of the MultiMediaCard, its environment, and handling. It also provides design guidelines and defines a tool box of macro functions and algorithms intended to reduce design-in ...Subject(s) : 4.2 , Electrical , Flash , MMC , MMCA , MultiMediaCard , Standard Capacity , -
JEDEC JESD76-3
Abstract: This standard continues the voltage specification migration to the next level beyond the 1.8 V specification already established. The purpose is to provide a standard for 1.5 V nominal supply voltage CMOS logic devices, ...Subject(s) : 1.5 V , CMOS ,