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JEDEC JESD82-10A

Definition of the SSTU32866 1.8 V Configurable Registered Buffer with Parity Test for DDR2 RDIMM Applications

Organization:
JEDEC - Solid State Technology Association
Year: 2007

Abstract: This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTU32866 registered buffer with parity test for DDR2 RDIMM applications. The purpose is to provide a standard for the SSTU32866 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.
URI: https://yse.yabesh.ir/std/handle/yse/178757
Subject: DDR2
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contributor authorJEDEC - Solid State Technology Association
date accessioned2017-09-04T17:55:34Z
date available2017-09-04T17:55:34Z
date copyright05/01/2007
date issued2007
identifier otherFKJEACAAAAAAAAAA.pdf
identifier urihttps://yse.yabesh.ir/std/handle/yse/178757
description abstractThis standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTU32866 registered buffer with parity test for DDR2 RDIMM applications. The purpose is to provide a standard for the SSTU32866 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.
languageEnglish
titleJEDEC JESD82-10Anum
titleDefinition of the SSTU32866 1.8 V Configurable Registered Buffer with Parity Test for DDR2 RDIMM Applicationsen
typestandard
page44
statusActive
treeJEDEC - Solid State Technology Association:;2007
contenttypefulltext
subject keywordsDDR2
subject keywordsRDIMM
subject keywordsRegistered Buffer
subject keywordsSSTU32866
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