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JEDEC JESD82-6A

Definition of the SSTV32852 2.5-V 24-Bit to 48-Bit SSTL_2 Registered Buffer for 1U Stacked DDR DIMM Applications

Organization:
JEDEC - Solid State Technology Association
Year: 2004

Abstract: This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTV32852 24-bit to 48-bit SSTL_2 registered buffer for stacked DDR DIMM applications. The purpose is to provide a standard for the SSTV32852 logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.
URI: https://yse.yabesh.ir/std/handle/yse/197445
Subject: DDR
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contributor authorJEDEC - Solid State Technology Association
date accessioned2017-09-04T18:14:31Z
date available2017-09-04T18:14:31Z
date copyright38292
date issued2004
identifier otherHHTPGBAAAAAAAAAA.pdf
identifier urihttps://yse.yabesh.ir/std/handle/yse/197445
description abstractThis standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTV32852 24-bit to 48-bit SSTL_2 registered buffer for stacked DDR DIMM applications. The purpose is to provide a standard for the SSTV32852 logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.
languageEnglish
titleJEDEC JESD82-6Anum
titleDefinition of the SSTV32852 2.5-V 24-Bit to 48-Bit SSTL_2 Registered Buffer for 1U Stacked DDR DIMM Applicationsen
typestandard
page18
statusActive
treeJEDEC - Solid State Technology Association:;2004
contenttypefulltext
subject keywordsDDR
subject keywordsDIMM
subject keywordsLow Profile
subject keywordsSDRAM
subject keywordsSSTV32852
subject keywordsStacked
subject keywordsSupport Logic
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