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JEDEC JESD82-5

Description of a 3.3 V, Zero Delay Clock Distribution Device Compliant with JESD21-C, PC133 Registered DIMM Specification

Organization:
JEDEC - Solid State Technology Association
Year: 2002

Abstract: This standard defines the PLL support devices required for standard height and low profile registered PC133 SDRAM DIMM modules. The objective of the standard is to clearly define the functionality, pinout and electrical characteristics of the PLL used on JEDEC standard modules.JESD82-5 is the latest specification to be added to the JESD82 family of specifications for memory module support devices. Additional specifications are currently under development for DDR2 support devices.
URI: https://yse.yabesh.ir/std/handle/yse/209088
Subject: DIMM
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    JEDEC JESD82-5

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contributor authorJEDEC - Solid State Technology Association
date accessioned2017-09-04T18:26:54Z
date available2017-09-04T18:26:54Z
date copyright07/01/2002
date issued2002
identifier otherIMRQZAAAAAAAAAAA.pdf
identifier urihttps://yse.yabesh.ir/std/handle/yse/209088
description abstractThis standard defines the PLL support devices required for standard height and low profile registered PC133 SDRAM DIMM modules. The objective of the standard is to clearly define the functionality, pinout and electrical characteristics of the PLL used on JEDEC standard modules.JESD82-5 is the latest specification to be added to the JESD82 family of specifications for memory module support devices. Additional specifications are currently under development for DDR2 support devices.
languageEnglish
titleJEDEC JESD82-5num
titleDescription of a 3.3 V, Zero Delay Clock Distribution Device Compliant with JESD21-C, PC133 Registered DIMM Specificationen
typestandard
page16
statusActive
treeJEDEC - Solid State Technology Association:;2002
contenttypefulltext
subject keywordsDIMM
subject keywordsMemory Modules
subject keywordsPC133
subject keywordsPLL
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