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Definition of the SSTU32865 Registered Buffer with Parity for 2R × 4 DDR2 RDIMM Applications

contributor authorJEDEC - Solid State Technology Association
date accessioned2017-09-04T18:30:44Z
date available2017-09-04T18:30:44Z
date copyright05/01/2007
date issued2007
identifier otherIWXDACAAAAAAAAAA.pdf
identifier urihttps://yse.yabesh.ir/std/handle/yse/212922
description abstractThis standard provides the functional definition, ball-out configuration and package outline, signal definitions and input/output characteristics for a 28-bit 1:2 registered driver with parity suitable for use on DDR2 RDIMMs. The SSTU32865 integrates the functional equivalent of two SSTU32864 devices (as defined in JESD82-7) into a single device, thereby easing layout and board design constraints especially on high density RDIMMs such as dual rank, by four configurations. Moreover, the optional use of a parity function is provided for, permitting detection and reporting of parity errors across its 22 data inputs. JESD82-9 specifies a 160-pin Thin-profile, fine-pitch ball-grid array (TFBGA) package.
languageEnglish
titleJEDEC JESD82-9Bnum
titleDefinition of the SSTU32865 Registered Buffer with Parity for 2R × 4 DDR2 RDIMM Applicationsen
typestandard
page26
statusActive
treeJEDEC - Solid State Technology Association:;2007
contenttypefulltext
subject keywordsDDR2
subject keywordsRDIMM
subject keywordsRegistered Buffer
subject keywordsSSTU
subject keywordsSSTU32865


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