JEDEC JESD36
Standard for Description of Low-Voltage TTL-Compatible, 5 V-Tolerant CMOS Logic Devices
Organization:
JEDEC - Solid State Technology Association
Year: 1996
Abstract: This standard outlines the standard dc specifications, test conditions, and test loading for logic products that are designed to tolerate input and output voltages which exceed the device's power supply. More specifically this standardizes 5 V Tolerant logic prducts that run from 'low voltage' (2.7 V to 3.6 V) power supplies. Products that meet this standard can be used to effectively interface between LVCMOS/LVTTL and 5 V TTL buses, bridging the gap between low-voltage and 5 V TTL busses
Subject: 5 V Tolerant - CMOS Devices
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contributor author | JEDEC - Solid State Technology Association | |
date accessioned | 2017-09-04T18:31:51Z | |
date available | 2017-09-04T18:31:51Z | |
date copyright | 06/01/1996 | |
date issued | 1996 | |
identifier other | IZUPCAAAAAAAAAAA.pdf | |
identifier uri | https://yse.yabesh.ir/std/handle/yse/214049 | |
description abstract | This standard outlines the standard dc specifications, test conditions, and test loading for logic products that are designed to tolerate input and output voltages which exceed the device's power supply. More specifically this standardizes 5 V Tolerant logic prducts that run from 'low voltage' (2.7 V to 3.6 V) power supplies. Products that meet this standard can be used to effectively interface between LVCMOS/LVTTL and 5 V TTL buses, bridging the gap between low-voltage and 5 V TTL busses | |
language | English | |
title | JEDEC JESD36 | num |
title | Standard for Description of Low-Voltage TTL-Compatible, 5 V-Tolerant CMOS Logic Devices | en |
type | standard | |
page | 13 | |
status | Active | |
tree | JEDEC - Solid State Technology Association:;1996 | |
contenttype | fulltext | |
subject keywords | 5 V Tolerant - CMOS Devices | |
subject keywords | CMOS Logic Device - TTL Compatible - CMOS Logic Devices | |
subject keywords | Low Voltage - CMOS Logic Devices |