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JEDEC JESD36

Standard for Description of Low-Voltage TTL-Compatible, 5 V-Tolerant CMOS Logic Devices

Organization:
JEDEC - Solid State Technology Association
Year: 1996

Abstract: This standard outlines the standard dc specifications, test conditions, and test loading for logic products that are designed to tolerate input and output voltages which exceed the device's power supply. More specifically this standardizes 5 V Tolerant logic prducts that run from 'low voltage' (2.7 V to 3.6 V) power supplies. Products that meet this standard can be used to effectively interface between LVCMOS/LVTTL and 5 V TTL buses, bridging the gap between low-voltage and 5 V TTL busses
URI: https://yse.yabesh.ir/std/handle/yse/214049
Subject: 5 V Tolerant - CMOS Devices
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    JEDEC JESD36

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contributor authorJEDEC - Solid State Technology Association
date accessioned2017-09-04T18:31:51Z
date available2017-09-04T18:31:51Z
date copyright06/01/1996
date issued1996
identifier otherIZUPCAAAAAAAAAAA.pdf
identifier urihttps://yse.yabesh.ir/std/handle/yse/214049
description abstractThis standard outlines the standard dc specifications, test conditions, and test loading for logic products that are designed to tolerate input and output voltages which exceed the device's power supply. More specifically this standardizes 5 V Tolerant logic prducts that run from 'low voltage' (2.7 V to 3.6 V) power supplies. Products that meet this standard can be used to effectively interface between LVCMOS/LVTTL and 5 V TTL buses, bridging the gap between low-voltage and 5 V TTL busses
languageEnglish
titleJEDEC JESD36num
titleStandard for Description of Low-Voltage TTL-Compatible, 5 V-Tolerant CMOS Logic Devicesen
typestandard
page13
statusActive
treeJEDEC - Solid State Technology Association:;1996
contenttypefulltext
subject keywords5 V Tolerant - CMOS Devices
subject keywordsCMOS Logic Device - TTL Compatible - CMOS Logic Devices
subject keywordsLow Voltage - CMOS Logic Devices
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