درباره ما
JEDEC - Solid State Technology Association: Recent submissions
Now showing items 161-180 of 369
-
JEDEC JESD22-A104D
Abstract: This standard provides a method for determining solid state devices capability to withstand extreme temperature cycling. Changes in this revision include requirements that the worst-case load temperature must reach the ...Subject(s) : Reliability Models , Temperature Cycling , Test Method - Temperature Cycling , -
JEDEC JESD371
Abstract: General
The measuring system must provide a means for applying bias to the transistor under test. The bias system must be such as not to influence the accuracy of the measurements, The signal applied ... -
JEDEC JEP179
Abstract: The purpose of this document is to explain the meaning of SPD setting (JESD21 SPD section) for DDR2 SDRAM (JESD79-2) in normal and extended temperature operationy67.Subject(s) : DDR2 , Refresh Operation , SPD , Temperature Range , -
JEDEC JEP123
Abstract: The need for this guideline arose from widespread lack of consistency in characterizing electrical parameters of electronic packages, which existed in the industry until the early 1990s. Then, the JEDEC Committee JC-15 ...Subject(s) : Capacitance Model , Inductance Model , Measurement - Package Inductance/Capacitance Model Parameters , -
JEDEC JES2
Abstract: Establishes guideline requirements and quality assurance provisions for gallium arsenide power field-effect transistors (FETs, also know as MESFETs) designed for use in high-reliability space application such as spacecraft ...Subject(s) : FETs - Field Effect Transistors , GaAs Power FETs , -
JEDEC JESD51-13
Abstract: This document provides a unified collection of the commonly used terms and definitions in the area of semiconductor thermal measurements. The terms and definitions provided herein extend beyond those used in the JESD51 ...Subject(s) : Definitions , Terms , Thermal Measurement , -
JEDEC JESD89A
Abstract: This specification defines the standard requirements and procedures for terrestrial soft-error-rate (SER)testing of integrated circuits and reporting of results. Both real-time (unaccelerated) and acceleratedtesting ...Subject(s) : Alpha Particles , Cosmic Rays , Soft Error Rate , Terrestrial , -
JEDEC JEP145
Abstract: This publication is intended as a guideline to establish procedures, consideration and common practices that will allow a manufacturer, an application entity, a system designer and other interested parties to define current ...Subject(s) : Current-Carrying Capability , Power Package , -
JEDEC JEP158
Abstract: To increase device bandwidth, reduce power and shrink form factor, microelectronics manufacturers are implementing three dimensional (3D) chip stacking using through silicon vias (TSVs). Chip stacking with TSVs combines ...Subject(s) : 3D , Connection , Reliabilty , Stack , Through-Silicon Via , Via , -
JEDEC JESD48C
Abstract: This standard is applicable to suppliers of, and affected customers for, solid-state products.
This standard establishes the requirements for timely customer notification of planned product discontinuance, which will ... -
JEDEC JEP139
Abstract: This document describes a constant temperature (isothermal) aging method for testing aluminum (Al) metallization test structures on microelectronics wafers for susceptibility to stress-induced voiding. This method is valid ...Subject(s) : Metal Voiding , Reliability , SIV , Stress , Stress Voiding , -
JEDEC JESD22-A100C
Abstract: The Cycled Temperature-humidity-bias Life Test is performed for the purpose of evaluating the reliability of nonhermetic packaged solid state devices in humid environments. It employs conditions of temperature cycling, ...Subject(s) : Bias Life , Cavity , Humidity , Lidded Ceramic , MQUAD , Temperature Cycling , Test Method - Cycled Temperature Humidity , -
JEDEC JESD99C
Abstract: Foreword
This standard will prove to be a useful guide for users, manufacturers, educators, technical writers, and others interested in the characterization, nomenclature, and classification of ... -
JEDEC JESD82-21
Abstract: This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a CUA845 PLL clock device for registered DDR2 DIMM applications.The purpose is to provide ...Subject(s) : CUA845 , DDR2 , DIMM , PLL , RDIMM , SO-CDIMM , -
JEDEC JESD282B.01
Abstract: This standard provided definitions, electrical characteristics circuit technology, letter symbols and registration format for diodes and stacks. It also covers rating and characteristics, manufacturing and performance as ... -
JEDEC JEP132
Abstract: This guideline provides a methodology to characterize a new or existing process and is applicable to any manufacturing or service process. It describes when to use specific tools such as failure mode effects analysis (FEMA), ...Subject(s) : Description - Problem Solving Tools , Problem Solving Tools , Process Characterization , -
JEDEC JESD22-A122
Abstract: This Test Method establishes a uniform method for performing component package power cycling stress test. This specification covers power induced temperature cycling of a packaged component, simulating the non-uniform ...Subject(s) : Cycling , Power , Power Cycle , Test Method , Test Method - Power Cycling , -
JEDEC JESD82-11
Abstract: This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a Â'CU878 PLL clock device for registered DDR2 DIMM applications. The purpose is to ...Subject(s) : Clock Driver , CU878 , DDR2 , DIMM , Fast Lock , PLL , -
JEDEC JESD73-2
Abstract: This standard covers specifications for a family of 3.3 V NMOS FET bus switch devices with integrated charge pumps. Not included in this document are device specific parameters and performance levels that the vendor must ...Subject(s) : Bus Switch , Charge Pump , NFET Switch , -
JEDEC JESD59
Abstract: This standard describes the modeling of a bond wire from an integrated circuit (IC) die to a package lead in a ball or wedge type wire bond configuration.Subject(s) : Bond Wire - Modeling , Modeling - Bond Wire ,